Low Power Ge-Si0.7 Ge0.3 nJLTFET and pJLTFET Design and Characterization in Sub-20 nm Technology Node

Suman Lata Tripathi, Sobhit Saxena,

Yogesh Kumar Verma and Manoj Singh Adhikari


Multi-gate MOSFET structures have emerged as a potential candidates for low power SoC or integrated circuits [1-5] to overcome the thermal limits imposed due to the scaling of transistors. A vertical p-channel and n-channel hetero-junction tunnel field effect transistor (TFET) has been proposed with the steep subthreshold slope and very small OFF-state current that are important design considerations while device scaling in sub 45 nm technology (Figure 11.1) [6, 7]. Narrow bandgap materials such as SiGe, Ge, and InAs reduce tunneling distance and enhance the band to band tunneling (BTBT) effect in TFET with a better ON- and OFF-state current ratio [8]. The band-to-band tunneling in TFET follows the charge-plasma concept that depends upon the work function difference of metallic gate contact to source/drain region. Also, the silicon body thickness must be less than the Debye length [4].

Debye length can be expressed mathematically by

Hetero-junction TFET based on III-V compounds

FIGURE 11.1 Hetero-junction TFET based on III-V compounds

where N denotes carrier concentration, eSi the dielectric constant of silicon, and VTh is constant with temperature and termed "thermal voltage.”

A thin SiGe pocket region is incorporated to reduce tunneling distance, which increases the BTBT of electrons, resulting in steep subthreshold characteristics [9,10]. Longer channel lengths are preferred in TFET [11-17] for better ON-state current. Junction-less tunnel FET with a silicon-on-insulator (SOI) box region shows an increase in ON and OFF to improved ION/IOFF ratio [ 18-21 ]. A small pocket Ge-Si0 7Ge0, n-channel junctionless TFET (nJLTFET) is proposed in which a thin Si07Ge03 region is incorporated with Ge as the source, drain, and channel material replacing Si. Ge is used in place of Si to exploit the advantage of a smaller bandgap (0.7 eV in comparison to 1.1 eV), which plays an important role in tunneling phenomena. The use of a thin pocket region toward the source side improves transfer characteristics by increasing the ON current. To increase channel mobility, the channel region is kept at a low doping profile in comparison to source-drain region doping. The doping of a thin pocket region is also kept high for nJLTFET. The proposed pocket Ge-Si()7Ge0, nJLTFET has been optimized in terms of gate contact and oxide region materials to obtain better ON/OFF performance along with sufficient ON current. Similarly, ultra-small Ge-Si0 7Ge0, p-channel junctionless TFET (pJLTFET) is also designed and characterized for different gate contact and oxide material as well as doping profile. In Ge-Si07Ge0, pJLTFET, the thin pocket region is kept at a low doping profile in comparison to Ge-Si0 7Ge0, nJLTFET, to match their ON- and OFF-state characteristics. The transfer characteristics of nJLTFET and pJLTFET were compared and both found suitable for implementation in complementary MOS (CMOS) technology.

Trransistors designed with nJLTFET and pJLTFET can be further implemented in the future with low-power design DRAM [22] cell and SRAM [23, 24] cells. This chapter deals with the design and analysis of Ge-Si07Ge03 nJLTFETs and pJLTFETs for low power, low voltage applications. The analysis is performed for DC and AC parameters including the effect of temperature on device ON/OFF-state performance.

Device Structures and Dimensions

The proposed Ge-Si0 7Ge0, nJLTFET has been implemented on the technology computer- aided design (TCAD) device simulator. Ge is used as a source, drain, and channel material replacing Si with the advantage of a lesser energy bandgap and higher tunneling rate. The three regions, source, drain, and channel, are doped with similar impurity atoms to make an n-type region, keeping source/drain doping at 1 x 1020 cnr3 and channel doping at 1 x 1016 cnr3. A local BTBT Kane’s model is followed along with the Shockley-Read-Hall (SRH) model for 2D/3D device simulation. The Lombardi model is used for mobility analysis in the presented simulation work. Kane’s tunneling model is used in the simulator to calculate the carrier generation by the band-to-band tunneling phenomenon.

Kane's [25] model can be expressed as tunneling generation rate as follows:

where E is the magnitude of the electric field and E„ the energy bandgap. A and В are constant parameters that depend on device structures and materials. The values of these two parameters are adjusted to match the experimental Id-Vgs characteristics.

Figure 11.2 describes the 2D and 3D Ge-Si07Ge0 , nJLTFET structure. A high workfunction Pt is used as gate contact material with a high value of work function

5.7 eV. High dielectric constant material HfO, (25) is used as an oxide region under the gate, replacing Si02 (dielectric constant = 3.9).

Figure 11.3 shows the energy-band diagram of Ge-Si07Ge03 nJLTFET obtained on visual TCAD simulation. The minimum of conduction and maximum of valance band are plotted against the changes in bias conditions. The changes observed in the conduction band are similar to those observed in the valance band, showing ideal behavior of the channel region in the proposed Ge-Si0 7Ge03 nJLTFET. The channel potential rises with an increase in gate bias voltage for a constant drain to source voltage, as shown in Figure 11.4.

Figure 11.5 indicates the electric field, with additional peaks in the source-pocket region. Figure 11.6 describes the variation of hole density in the pocket region, depending on the gate and drain bias conditions. High hole density in the OFF-state condition offers less effect of the parasitics. The proposed Ge-Si07Ge03 nJLTFET achieves better switching speed with a low value of hole density in the ON-state. Therefore, the proposed Ge-Si07Ge03 nJLTFET supports parasitic BJT triggering between the source-channel region in the ON-state.

D view of pocket SiGe, JLTFET with Ge wafer

FIGURE 11.2 2D view of pocket Si07Ge0, JLTFET with Ge wafer

Energy-band diagram of Ge-Si07Ge0 3 nJLTFET along its x-axis


Channel potential of Ge-SiGe nJLTFET along its x-axis

FIGURE 11.4 Channel potential of Ge-Si07Ge03 nJLTFET along its x-axis

Electric field of Ge-SiGe, nJLTFET along its x-axis

FIGURE 11.5 Electric field of Ge-Si07Ge0, nJLTFET along its x-axis

Hole density of Ge-SiGe, nJLTFET along its x-axis

FIGURE 11.6 Hole density of Ge-Si07Ge0, nJLTFET along its x-axis

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