RF/Analog and Linearity Performance Evaluation of a Step-FinFET under Variation in Temperature

Rajesh Saha

Malaviya National Institute of Technology Jaipur

Brinda Bhowmick and Srimanta Baishya

National Institute of Technology Silchar

Introduction

Scaling of MOSFETs provides an enormous improvement in switching speed, packing density, and cost of microprocessors, which leads to increased number of transistors and hence increased power density [1]. However, to fulfil the industrial demands, scaling of MOSFETs leads to several unwanted issues such as huge subthreshold swing (SS), large amount of drain-induced barrier lowering (DIBL), large leakage current, etc. and these need to be addressed [2,3]. To address these issues, various engineering techniques such as material change, gate structure change, modification of work function, modification of device architecture, use of spacers, change of gate oxide material, etc. have emerged over time [4-6]. Combination of these techniques has led to emerging devices that can replace MOSFETs. In this regard, FinFETs present themselves as challengers capable of overcoming the adverse short-channel effects

(SCEs), and here, the conducting channel is wrapped by all three sides of the gate [7,8]. They are categorized as multi-gate MOSFETs, where the vertical fin is placed between source and drain regions. A large number of articles on analytical modelling and simulation of electrical parameters in FinFETs are reported in the literature. The performance of FinFETs is also improved by various modified FinFET architectures such as cylindrical FinFETs [9], FinFETs with a gate structure like pie [10], omega structured FinFETs [11], FinFETs with a gate made of two different gate materials named dual material gate (DMG) FinFETs [12], likewise triple material gate (TMG) FinFETs [13], and many more. We have reported a step-like fin structure named step- FinFET, and its electrical performance for different fin dimensions is analysed [14]. Further, circuit realizations of devices are extremely essential, and therefore, study on circuit parameters in FinFETs is important. A number of studies are available in the literature on the analog/RF performance of MOS devices [15-17], a quadruple gate-all-around (GAA) MOSFET [18], a junctionless FinFET [19], and DMG/TMG FinFETs [20]. Experimental demonstration of the analog/RF parameters of FinFETs exists in the literature [21]. On the other hand, temperature is one major factor that has a significant impact on device performance, and therefore, it is very important that the performance of a device sustains under variation in temperature. A simulation study of RF/analog performance of DMG FinFETs is reported with variation in temperature [22]. The study also investigated the linearity characteristics of DMG FinFETs. Therefore, analysis of temperature effect on RF/analog as well as linearity parameters of other non-conventional FinFET architectures is one of the attractive research areas.

This chapter presents the temperature effects on RF/analog figures of merit (FOMs): transconductance (gj, total gate capacitance (Cgg), output conductance (gd), transconductance generation factor (TGF = g„,/ID), cut-off frequency (/,), intrinsic gain (gjgd), and gain transconductance frequency product (GTFP) for a step-FinFET through a Sentaurus 3D Technology Computer Aided Design (TCAD) simulator. Linearity parameters such as higher order harmonics (gm2 and gmJ), voltage intercept points (VIP2 and VIP3), third order power intercept point (IIP,), and third order intermodulation distortion (IMD,) are discussed by changing the temperature from 250 to 450 К with a step of 50 K. We also present the transfer characteristics and the current ratio of a step-FinFET by varying the temperature.

Literature Survey

Raskin et al. reported a fair investigation of the RF/analog performance by changing the number of gates, that is, single gate (SG), double gate (DG), and triple gate (TG) MOSFETs, and modifying the gate structure, such as pie and omega gate MOSFETs, through 3D simulations for wideband applications [16]. It is reported that as the number of gate increases better RF/analog performance is obtained than for a SG device, and this is due to a large amount of early voltage, which leads to improved intrinsic gain. Subramanian et al. investigated the comparative analysis of RF performance between FinFETs and bulk MOSFETs [17]. They have summarized that at low-frequencies FinFETs show good RF performance, whereas at high- frequencies MOSFETs have improved RF characteristics.

An analytical model for various analog/RF FOMs such as intrinsic gain, capacitance, transconductance, output resistance, maximum frequency, and oscillation frequency of a quad gate GAA MOSFET has been developed by Sharma and Vishvakarma. They have found a close agreement of analytical data with simulation results obtained from an ATLAS TCAD simulator [18].

Jegadheesan et al. investigated the stability of RF performance with variation in temperature, fin width, fin height, and channel doping in Silicon on Insulator (SOI) junctionless FinFETs [19]. With increased temperature, maximum frequency and the stability of junctionless FinFETs reduce. However, as channel doping and fin dimensions increase, the maximum cut-off frequency increases, whereas the stability of junctionless FinFETs degrades. Lederer et al. showed that the RF performance of FinFETs varies by changing the gate length and fin width [21]. Results reveal that as the fin width reduces, the cut-off frequency decreases, and this is because of an increase in parasitic resistance with decreased fin width. Kumar reported a comparative study of RF/analog parameters among TG FinFETs, cylindrical GAA (CY-GAA) FinFETs, and rectangular GAA (RE-GAA) FinFETs [23] obtained through simulation. They concluded that CY-GAA FinFETs are suitable for RF applications as they have maximum capacitance, whereas RE-GAA FinFETs are suitable for analog applications as they have the highest transconductance.

Analytical design guidelines for RF/analog application of FinFETs were suggested by Sohn et al. [24], who reported that the RF performance can be improved by decreasing the ratio of fin-spacing to fin height. This is because cutoff and maximum frequencies are more influenced by reducing parasitic resistance than by increasing series resistance. Tinoco et al. discussed the RF behaviour of FinFETs due to variation in extrinsic gate capacitances [25]. They have reported that the RF performance is enhanced significantly by decreasing the fin spacing, modifying the ratio of fin height to width of the fin, and optimizing the ratio of fin spacing to extension source/drain regions of the fin. The RF stability performance at particular bias and device dimensions of FinFETs exists in the literature [26]. They have reported the optimized spacer length of the gate region, fin height, and fin width as well as have chosen appropriate work function for the gate material and bias settings to obtain better stability performance of FinFETs in the RF range.

Krivec et al. investigated the RF performance of bulk and SOI FinFETs with a gate length of 20 nm for both doped and undoped channels [27]. The cut-off frequency is more for bulk-substrate based FinFETs than for SOI FinFETs, whereas the maximum oscillation frequency is higher in SOI substrate FinFETs than in bulk substrate FinFETs. Mohapatra et al. presented a study on the impact of fin dimensions (fin width and height) on various RF/analog parameters of FinFETs [28] and depending on the feature ratio (fin width to height ratio), they act as FinFETs and trigate and planar MOSFETs. They systematically presented both low-frequency and high- frequency performance parameters of these devices.

A comparative study of RF/analog/linearity performance among conventional FinFETs (conv. FinFETs), DMG FinFETs, and TMG FinFET is realized through a TCAD simulator. Analysis reveals that DMG and TMG FinFETs have improved high-frequency and analog performances compared to conv. FinFETs [20], which is due to improved gate control with an increase in the number of gate materials.

Also, DMG and TMG FinFETs exhibit enhanced linearity performance compared to conv. FinFETs. Saha et al. reported that RF/analog and linearity characteristics of DMG FinFETs are a function of temperature. RF parameters degrade, whereas an improvement in linearity performance is visualized with the rise in temperature of DMG FinFETs [22]. For the variation of metal gate work function (фл/), high- frequency and analog performances of a multifin-FinFET are reported. It is seen that f, and the intrinsic gain of the multifin-FinFET improve with an increase in the work function of the gate material [29].

The RF performance of an NC-FinFET is reported in the literature, and it is found that the RF performance is a function of the ferroelectric layer thickness [30]. As the thickness of the ferroelectric layer increases, the RF performance such as gain and maximum frequency of the NC-FinFET degrade. Also, at lower values of supply voltage, the RF/analog performance of the NC-FinFET is similar to that of conv. FinFETs.

 
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