Summary

Table of Contents:

This chapter considered processing technologies for passive components, active devices and ICs. Four major IC technologies based on the bipolar transistor, the MOS-FET, CMOS, Bi-CMOS and FinFET were discussed in detail. It appears that the FinFET will be the dominant technology at least until 2025 because of its superior performance compared with the peer component. For 100 mn CMOS technology, a good candidate is the combination of an SOI substrate with interconnections using Cu and low-к materials.

Problems

  • 1. With a neat sketch explain BiCMS fabrication.
  • 2. Describe various steps in fabrication of CMOS.
  • 3. Discuss N-well process for CMOS fabrication.
  • 4. Discuss advantage of CMOS over bipolar devices.
  • 5. An n well process has thin oxide, n-well and n-plus masl layers, in addition to the other regular layers. Draw the mask combinations to obtain an n transistor, a p-transistor contact, a VDD contact and a Vss contact.

References

  • 1. S. Wolf, “Silicon Processing for the VLSI Era, Vol 3,” The Submicron MOSFET, Lattice Press, Sunset Beach, CA, (1995).
  • 2. S.M. Sze, “Physics of Semiconductor Devices,” Wiley, New York, (1981).
  • 3. E.H. Nicollian and J.R. Brews, “Metal Oxide Semiconductor Physics and Technology’, ” Wiley, New York, (1982).
  • 4. Y.P. Tsividis, “Operation and Modeling of the MOS Transistor,” McGraw- Hill, New York, (1987).
  • 5. F.M. Wanlass and C.T. Sail, “Nanowatt Logic Using Field-Effect Metal- Oxide-Semiconductor Triodes,” IEEE Int. Solid-State Circuits Conf, (1963).
  • 6. J.Y. Chen, “CMOS Devices and Technology for VLSI,” Prentice-Hall, Englewood Cliffs, NJ, (1989).
  • 7. R. Chwang and K. Yu, “CMOS—An n-Well Bulk CMOS Technology for VLSI,” VLSI Design, 42 (1981).
  • 8. L.C. Parrillo, L.K. Wang, R.D. Swenumson. R.L. Field, R.C. Melin, and R.A. Levy, “Twin-Tub CMOS II,” IEDMTech. Dig. 706 (1982).

9. R.H. Dennard, F.H. Gaensslen, H.N. Yu, V.L. Rideout, E. Barsous and A.

R. LeBlanc, “Design of Ion-Implanted MOSFETs with Very Small Physical Dimensions,” IEEE J. Solid-State Circuits SC, 9:256 (1974).

  • 10. Y. El Maney, “MOS Device and Technology Constraints in VLSI,” IEEE Trans. Electron Dev.ED, 29:567 (1982).
  • 11. J.R. Brews, W. Ficlitner, E.H. Nicollian, and S.M. Sze, “Generalized Guide for MOSFET Miniaturization,” IEEE Electron Devices Lett. EDL 1:2 (1980).
  • 12. M.H. White, F. Van de Wiele, and J.P. Lambot, “High-Accuracy Models for Computer-AidedDesign,” IEEE Trans. Electron Dev ED, 27:899 (1980).
  • 13. P.L. Suciu and R.I. Johnston, “Experimental Derivation of the Source and Drain Resistance of MOS Transistors,” IEEE Trans. Electron Dev. ED, 27:1846(1980).
  • 14. M.C. Jeng, J.E. Chung, P.K. Ко, and C. Hu, “The Effects of Source/ Drain Resistance on Deep Submicrometer Device Performance,” IEEE Trans. Electron Dev. 37:2408 (1990).
  • 15. C.Y. Lu, J.M.J. Sung, RLiu, N.S. Tsai, R. Singh, S.J. Hillenius, and G. C. Kirsch, “Process limitation and Device Design Trade-offs of SelfAligned TiSi, Junction Formation in Submicrometer CMOS Devices,” IEEE Trans. Electron Dev. 38:246 (1991).
  • 16. B. Davari, W.H. Chang, K.E. Petrillo, C.Y. Wong, D. Moy, Y. Taur, M.W. Wordeman, J.Y.C. Sun, C.C.H. Hsu, and M.R. Polcari, “A High Performance 0.25 nun CMOS Technology: II—Technology,” IEEE Trans. Electron Dev 39:967 (1992).
  • 17. S. Nygren and F. d’Heiule, “Morphological Instabilities in Bilayers Incorporating Polycrystalline Silicon,” Solid State Phenom. 23&24:81 (1992).
  • 18. A. Ohsaki, J. Komori, T. Katayama, M. Shimizu, T. Okamoto, H. Kotani, and

S. Nagao, “Thermally Stable TiSi2 Thin Films by Modification in Interface and Surface Structures,” Ext. Absstr. 21st SSDM, 13 (1989).

  • 19. C.Y. Ting, F.M. d'Heurle, S.S. Iyer, and PM. Fryer, “High Temperature Process Limitationson TiSi2,” J. Electrochern. Soc. 133:2621 (1986).
  • 20. H. Sumi, T. Nishihara, Y. Sugano, H. Masuya, and M. Takasu, “New Silicidation Technology by SITOX (Silicidation Through Oxide) and Its Impact on Sub-Half-Micron MOS Devices,” Proc. IEDM, 249 (1990).
  • 21. F.C. Shone, K.C. Saraswat and J.D. Plummer, “Formation of a 0.1 m n/p and p/n Junction by Doped Silicide Technology,” IEDM Tech. Dig., 407 (1985).
  • 22. R. Liu, D.S. Williams, and W.T. Lynch, “A Study of the Leakage Mechanisms of Silicided n+/p Junctions,” J. Appl. Phys. 63:1990 (1988).
  • 23. M.A. Alperin, T.C. Holloway, R.A. Hakeu, C.D. Gosmeyer, R.V. Karnaugh, and W.D. Pannantie, “Development of the Self-Aligned Titanium Silicide Process for VLSI Applications,” IEEE J. Solid-State Circuits SC, 20:61 (1985).
  • 24. R. Pantel, D. Levy, D. Nicholas, and J.R Ponpon, “Oxygen Behavior During Titanium Silicide Formation by Rapid Thermal Annealing,” J. Appl. Phys. 62:4319(1987).
  • 25. D.B. Scott, W.R. Hunter, and H. Shichijo, “A Transmission Line Model for Silicided Diffusions: Impact on the Performance of VLSI Circuits,” IEEE Trans. Electron Dev. ED, 29:651 (1982).
  • 26. P. Liu, T.C. Hsiao, and J.C.S. Woo, “A Low Thermal Budget Self-Aligned Ti Silicide Technology Using Germanium Implantation for Thin-Film SOI MOSFETs,” IEEE Trans. Electron. Dev. 45(6): 1280 (1998).
  • 27. J.A. Kittl and Q.Z. Hong, “Self-aligned Ti and Co Silicides for High Performance sub-0.18_mCMOS Technologies,” Thin Solid Films 320:110 (1998).

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