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FinFET Devices for VLSI Circuits and Systems

Fin Field-Effect Transistors Overview of MOSFET Devices for Integrated Circuit Manufacturing Challenges of MOSFET Scaling at the Nanometer Node Leakage Current in Short Channel MOSFETs Variability in MOSFETs Physics of MOSFET Scaling Challenges Alternative Device Concepts Undoped or Lightly Doped Channel MOSFETs Deeply Depleted Channel MOSFETs Buried-Halo MOSFETs Thin-Body Field-Effect Transistors Single-Gate Ultrathin-Body Field-Effect Transistors Multiple-Gate Field-Effect Transistors FinFET Devices for VLSI Circuits and Systems A Brief History of FinFET Devices Summary References Fundamentals of Semiconductor Physics Introduction Semiconductor Physics Energy Band Model Carrier Statistics Intrinsic Semiconductors Intrinsic Carrier Concentration Effective Mass of Electrons and Holes Extrinsic Semiconductors Fermi Level in Extrinsic Semiconductor Fermi Level in Degenerately Doped Semiconductor Electrostatic Potential in Semiconductor and Carrier Concentration Quasi-Fermi Level Carrier Transport in Semiconductors Drift of Carriers: Carrier Motion in Electric Field Diffusion of Carriers Generation-Recombination of Carrier Injection Level Recombination Processes Basic Semiconductor Equations Poisson’s Equation Transport Equations Continuity Equations Theory of n-Type and p-Type Semiconductors in Contact Basic Features of рn-Junctions Built-in Potential Step Junctions Electrostatics pn-Junctions under External Bias One-Sided Step Junction Carrier Transport Across pn-Junctions Relationship between Minority Carrier Density and Junction Potential рn-Junctions I - V Characteristics Temperature Dependence of pn-Junction Leakage Current Limitations of pn-Junction Current Equation Bulk Resistance Junction Breakdown Voltage pn-Junction Dynamic Behavior Junction Capacitance Diffusion Capacitance Small-Signal Conductance pn-Junction Equivalent Circuit Summary References Multiple-Gate Metal-Oxide-Semiconductor (MOS) System Introduction Multigate MOS Capacitors at Equilibrium Properties of Isolated Metal, Oxide, and Semiconductor Materials Workfunction Metal, Oxide, and Semiconductor Materials in Contact Forming MOS Systems MOS Systems with MG Workfunction at Silicon Band-Edges MOS Systems with Silicon-Midgap MG Workfunction Oxide Charges Effect of Oxide Charges on Energy Band Structure: Flat Band Voltage Surface Potential MOS Capacitor Under Applied Bias Accumulation Depletion Inversion Multigate MOS Capacitor Systems: Mathematical Analysis Poisson’s Equation Electrostatic Potentials and Charge Distribution Induced Charge in Semiconductor Formulation of Surface Potential Threshold Voltage Surface Potential Function Unified Expression for Inversion Charge Density Quantum Mechanical Effect Summary References Overview of FinFET Device Technology Introduction FinFET Manufacturing Technology Bulk-FinFET Fabrication Well Formation Fin Patterning: Spacer Etch Technique Alternative Well Formation Process Gate Definition: Polysilicon Dummy Gate Formation Source-Drain Extensions Processing Raised Source-Drain Processing Replacement Metal Gate Formation Self-Aligned Contact Formation. Metallization SOI-FinFET Process Flow Fin Patterning: Spacer Etch Technique Comparison of Bulk-Silicon FinFET and SOI-FinFET Fabrication Technology Summary References Large Geometry FinFET Device Operation Introduction Basic Features of FinFET Devices FinFET Device Operation Drain Current Formulation Derivation of Electrostatic Potential Continuous Drain Current Equation for Symmetric DG-FinFETs Regional Drain Current Formulation for Symmetric DG-FinFETs Threshold Voltage Formulation Linear Region lds Equation Saturation Region Ids Equation Subthreshold Conduction Summary References Small Geometry FinFETs Physical Effects on Device Performance Introduction Short-Channel Effects on Threshold Voltage Formulation of Natural Length Channel Potential Threshold Voltage Roll-Off DIBL Effect on Threshold Voltage Quantum Mechanical Effects Volume Inversion QM Effect on Mobility QM Effect on Threshold Voltage QM Effect on Drain Current Surface Mobility High Field Effects Velocity Saturation Channel Length Modulation Output Resistance Summary References Leakage Currents in FinFETs Introduction Subthreshold Leakage Currents Gate-Induced Drain and Source Leakage Currents Formulation of Gate-Induced Drain Leakage Current Formulation of Gate-Induced Source Leakage Current Impact Ionization Current Source-Drain pn-Junction Leakage Current Gate Oxide Tunneling Leakage Currents Summary References Parasitic Elements in FinFETs Introduction Source-Drain Parasitic Resistance Raised Source-Drain FinFET Structure Components of Source-Drain Series Resistance Contact Resistance Spreading Resistance Source-Drain Extension Resistance Gate Resistance Parasitic Capacitance Elements Gate Overlap Capacitance Fringe Capacitance Fin-to-Gate Fringe Capacitance Gate-to-Contact Fringe Capacitance Source-Drain pn-Junction Capacitance Reverse-Bias Capacitance Forward Bias Capacitance Summary References Challenges to FinFET Process and Device Technology Introduction Process Technology Challenges Lithography Challenges ArF Lithography with Multi-Patterning Extreme Ultraviolet Lithography Process Integration Challenges Precise and Uniform Fin Patterning Gate and Spacer Patterning Uniform Junction Formation in Fin Stress Engineering High-k Dielectric and Metal Gate Variability Control Spatial Challenges Dopant Implantation Challenges The Etching Challenges Device Technology Challenges Multiple Threshold Voltage Devices Width Quantization Crystal Orientation Source-Drain Series Resistance Challenges in FinFET Circuit Design Summary References FinFET Compact Models for Circuit Simulation Introduction Compact Device Model Common Multiple-Gate Compact FinFET Model Core Model Electrostatics Drain Current Model Modeling Real Device Effects Short-Channel Effects Quantum Mechanical Effects Mobility Degradation Velocity Saturation Source-Drain Series Resistance Dynamic Model Common Multigate C – V Model Threshold Voltage Variability Summary References

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