Alternative Device Concepts
In order to overcome the increasing challenges in continuous scaling of the conventional planar MOSFET devices, the major research and development efforts for the
FIGURE 1.7 A conventional MOSFET device showing the sub-surface leakage path between the source and drain; the sub-surface leakage cannot be controlled by scaling gate oxide thickness in nanometer node devices due to Cdsc which becomes comparable or higher than Cox to control the channel potential.
FIGURE 1.8 Lowering of source-to-channel potential in an «-channel device due to drain bias Vds: (a) = 0 and Vds = 0; (b) Vp = 0 and Vds = supply voltage, Vdd; (c) plot of conduction
band along the length of the device under zero-bias (top curve) and at drain-bias conditions (bottom curve).
last two decades have been to explore alternative device architectures [9,27,56-61] for VLSI manufacturing technology at the nanometer nodes. In Section 1.3.1, we briefly review the device options for continued scaling of planar-CMOS technology and thin-body devices as an alternative to conventional planar-CMOS technology.
Undoped or Lightly Doped Channel MOSFETs
Deeply Depleted Channel MOSFETs
Recently, advanced channel engineering has been developed to design nanoscale MOSFET devices with undoped or lightly doped channel to reduce the effect of RDD as shown in Figures 1.9 . The channel is formed on an undoped epitaxial layer grown on silicon substrate followed by standard CMOS processing
FIGURE 1.9 Deeply depleted channel MOSFET: In the schematic, region 1 is the undoped channel of the device, whereas, 2, 3, and 4 are the V„,-control, SCE suppression, and anti- punchthrough channel-type doped impurity layers, respectively.
steps [62,63]. This bulk-MOSFET structure is referred to as the deeply depleted channel (DDC) MOSFETs .
The DDC device shown in Figure 1.9 controls the process variability using undoped or lightly doped channel and suppresses the sub-surface leakage current by reducing Cdsc using heavily doped channel-type doping layers 2 and 3 deep into the channel .
In a planar-CMOS technology, a lightly doped channel is used in conjunction with a heavily doped channel-type implant, referred to as the “halo doping,” around the source-drain to reduce sub-surface leakage . The reported data show that the device architecture using two halo doping profiles, referred to as the “double-halo MOSFETs,” reduces the leakage current as well as controls V„, variation in nanoscale devices [5,9,42-44]. Recently, a variability-tolerant double-halo MOSFET device architecture shown in Figure 1.10 has been invented to design undoped or lightly doped channel MOSFETs on undoped epitaxial layer to suppress SCEs and mitigate the risk of process variability in devices of planar-CMOS technology [64,65]. This new double-halo structure is referred to as the “buried-halo MOSFET" (BFI-MOSFET). In BH-MOSFET architecture, well, optional V„,-adjust, and multiple halo implants are performed on bulk-silicon substrate prior to growing epitaxial-channel layer as shown in Figure 1.10, and the gate patterning and source-drain processing steps are performed after the epitaxy [64,65]. The reported data on ^-variability clearly show a significant reduction in V,;, variation due to RDD in nanoscale BH-MOSFETs compared to the conventional MOSFET devices [9,47,64].
FIGURE 1.10 Buried-halo MOSFET device structure formed by up-diffusion of multiple halo implant profiles in the undoped epitaxial layer from silicon substrate; in the fabrication process, a heavily doped first halo is used around the source-drain extension (SDE) regions to suppress leakage paths near the silicon-surface closer to the gate and a lightly doped second halo is used around the deep source-drain (DSD) regions to suppress leakage paths far from the gate, whereas the undoped epitaxial channel reduces the process variability in devices.
Figure 1.11 shows the estimated Vth variability of the conventional and BH-MOSFET devices of a typical 20 nm planar-CMOS technology down to Lg = 5 nm [9,47,64]. The data clearly show a significant reduction in V„, variation due to RDD in nanometer scale BH-MOSFETs compared to the conventional MOSFET devices.
Thin-Body Field-Effect Transistors
The novel device architecture to ensure greater gate control of the channel for FET devices is to use thin-body silicon as the channel. There are two ways to enhance the gate control of the body and reduce the drain control of the channel and Cjsc by (1) ultrathin body on an SOI substrate as described in Section 220.127.116.11 and (2) multiple gates around an ultrathin-body silicon channel as described in Section 18.104.22.168 .
Single-Gate Ultrathin-Body Field-Effect Transistors
The SCEs in a MOSFET can be significantly suppressed by using an ultrathin SOI substrate  to bring silicon closer to the gate. However, the improvement of SCEs in MOSFETs on SOI substrates depends on the technology parameters such as silicon film thickness tsi, gate-dielectric (silicon dioxide) thickness, and body doping concentration. The reported data show that the leakage current decreases with a decrease of tsi [67,68]. And, by reducing tsi to only around 7 to 14 nm, SCEs can be significantly suppressed by eliminating the worst leakage paths terminated in the buried silicon dioxide as shown in Figure 1.12 [67,68]. Furthermore, ultrathin-body FETs
FIGURE 1.11 Buried-halo MOSFETs: Comparison of the simulated threshold voltage variation of the conventional (Std-MOS) and BH-MOSFET (BH-MOS) devices of a typical 20-nm bulk-CMOS technology as a function of the channel length for channel width 20 and 200 nm.
FIGURE 1.12 Ultrathin-body MOSFETs on SOI substrate: The structure shows that for an appropriate thickness of silicon, tsl body, the sub-surface leakage path is terminated in the buried oxide, thus suppressing the leakage current.
on undoped or lightly doped substrate reduces variability. The ultrathin-body FETs on SOI substrate, referred to as the UTB-SOI-MOSFETs, have emerged as one of the most promising devices for advanced VLSI circuits at the nanometer node [66-71].
Multiple-Gate Field-Effect Transistors
The SCEs can be more effectively controlled by using multiple gates, referred to as the multigate around the silicon body or channel of a MOSFET. Figure 1.13 shows a
FIGURE 1.13 Double-gate MOSFETs: A thin silicon body with gates at the top and bottom of the silicon body to provide complete gate control of the body from the top and bottom, thus eliminating the sub-surface leakage paths. Here tsi is the thickness of the silicon body.
typical FET device with a thin silicon body and two gates; one above and the other below' the body. For such a double-gate (DG) FET device with thin body shown in Figure 1.13, the potential leakage paths far from the top gate are closer to the bottom gate eliminating the potential sub-surface leakage far from the top gate; and the leakage paths far from the bottom gate are closer to the top gate, thus eliminating the leakage paths far from the bottom gate or sub-surface leakage. Thus, a DG-MOSFET offers stronger electrostatic control of the inversion channel by the gates above and below' the silicon body. And, therefore, reduces the SCEs and makes the multigate FETs more scalable than the planar-CMOS devices on bulk substrate [72,73].
Thin-body architecture (Figure 1.13) also eliminates the requirement for heavy channel doping for suppressing SCEs contrary to the conventional scaling principle. Optional channel doping may be used to adjust V„, to the target specification instead of gate metal w'orkfunction engineering [9,27]. The undoped or lightly doped thin body as the channel reduces RDD in multigate FETs and therefore, the variability in device performance can be eliminated. Furthermore, an undoped or lightly doped body reduces the average electric field in the channel which translates to an improvement in the carrier mobility, gate leakage currents, and device reliability. This, potentially, improves the bias-temperature stability (negative-bias temperature instability and positive-bias temperature instability) and the gate-dielectric tunneling leakage and wear out . The combination of the light body doping and thin body offers steeper subthreshold swing and lower junction and body capacitances .
From the above discussions, we find that a thin-body DG-MOSFET structure shown in Figure 1.13 shows great potential to control SCEs and suppress leakage current by keeping the gate closer to the silicon body and reduce process variability. Then by rotating the DG-structure by 90 degrees to make it a vertical DG-MOSFET standing on a silicon or SOI substrate, it would be possible to achieve the lowest possible gate leakage current w'ith self-aligned gates. Such a vertical DG-MOSFET with thin “fin”-like body structure is referred to as the “FinFET,” as shown in Figure 1.14 and described in Section 1.4.