Non-Conventional Solutions to Miniaturization Problems

Silicon-On-Insulator

The channel formation in a MOSFET takes place in few micrometers below the oxide. The thickness of substrate is kept much greater than that to ensure the structural feasibility of the device. However, this unused substrate adds several para- sitics and contributes to leakage currents directly from source and drain regions [25]. In addition, the unused substrate reduces the mobility of the charge carriers. These effects aggravate especially with higher body doping and small dimensions. To maintain the structural feasibility and eliminate these effects, an insulating layer is added within the body of substrate as shown in Figure 5.2. Such a technique is called

SOI MOSFET device structure

FIGURE 5.2 SOI MOSFET device structure.

silicon-on-insulator (SOI) technology. Depending upon whether the depletion region of the channel consumes the silicon depth between the oxides partially or fully, the SOI MOSFETs are categorized as partially depleted SOI (PD-SOI) MOSFETs and fully depleted SOI (FD-SOI) MOSFETs. The buried oxide (BOx) layer within the substrate offers low parasitics, removes the leakage paths, and enables the high speed of operation. Besides, SOI platform offers enhanced channel mobility, avoids device latch-up, reduces random dopant fluctuation, and decreases variability in threshold voltage [26,27]. However, the main problem in SOI is the self-heating and therefore prone to heat accumulation as the thermal conductivity of Si02 is about two orders of magnitude less than silicon [28]. Replacing Si02 with air (silicon-on-nothing (SON)) has been proposed as an alternate solution for advanced scalability due to better heat dissipation and good control of the fringing fields [29,30].

Multigate MOSFET

The MOSFET has been scaled into nanoregime to maintain the performance predicted by International Technology Roadmap for Semiconductors (ITRS) while at the same time achieving ultra-large-scale-integration (ULSI) implementation [31]. To avoid the non-ideal effects and electrostatic limitations, several techniques have been proposed by the researchers. Besides, in order to increase the control of gate over the channel, thin oxides or high-к dielectrics were proposed. However, the problem with thin oxides or high-к dielectrics is their structural instability and difficulty of fabrication [32]. Colinge in 2004 pointed out that electrostatic control of gate over the channel can be enhanced by using multiple gates while at the same time using thicker oxides [33]. Based on the number of gates used, the multigate MOSFETs are divided into double-gate (DG), trigate (TG), and surrounding gate (SG) or gate-all-around (GAA) MOSFETs. The multigate transistors are considered as the future for mitigating the problems of conventional nanoscale MOSFETs [34]. To avoid the undesirable short channel effects, multiple gates can be used instead of high doping in the channel.

Double-Gate (DG) MOSFET

The planar DG MOSFET proposed by Sekigawa and Hayashi in 1984 is shown in Figure 5.3 [35]. As shown in the figure, one gate is placed on the top of the channel and the other gate at the bottom of the channel. Depending upon whether the depletion regions formed by top and bottom gates consumed full or partial thickness of silicon between oxides, the MOSFET is divided into FDDG MOSFET and PDDG MOSFET. In case, the full silicon thickness is not consumed, two channels are formed near the two oxides. However, if the silicon thickness is fully consumed, the channel formation takes place at the middle of the silicon channel and thus avoids scatterings at oxide surfaces [36]. This leads to the high mobility of carriers in the channel and consequently higher transconductance and drive current. The DG MOSFETs are more resistant to short channel effects than conventional bulk MOSFETs [37]. However, implementing DG MOSFETs is difficult as maintaining double-gate symmetry is a serious technology challenge. Therefore, a nonplanar DG MOSFET device called FinFET was proposed which promises performance and scalability in nanoregime and at the same time eliminates the technology barrier of planar DG MOSFET [38].

Trigate (TG) MOSFET

TG MOSFET was first proposed by Doyle et al. in 2003. The channel is surrounded by gate from three sides [39]. The SOI version of TG MOSFET was reported by Colinge and is shown in Figure 5.4 [40]. Unlike the DG MOSFETs, the TG MOSFET does face the problem of gate symmetry and has better current drive than DG MOSFET

Trigate SOI MOSFET structure

FIGURE 5.4 Trigate SOI MOSFET structure.

due to the formation three conduction channels. Besides, it offers better immunity to short channel effects than DG MOSFET [41]. To avoid the corner effects, the triangular and trapezoidal versions of TG MOSFETs have also been reported [42].

Gate-All-Around (GAA) MOSFET

The channel GAA MOSFET is surrounded by gates from all sides. Based on their shapes, GAA MOSFETs are categorized as square-, rectangular-, and circular-shaped GAA MOSFETs as shown in Figure 5.5 [43-45]. GAA MOSFETs provide better seal- ability and avoid short channel effects. Since the channel is surrounded by gates from all sides, the GAA MOSFET provides ideal subthreshold swing [46]. If the thickness of the channel is of few atoms, then rectangular- and circular-shaped GAA transistors are called nanosheet (NS) MOSFET and nanowire (NW) MOSFET, respectively.

Gate and Channel Engineering Techniques

Gate-Oxide Stack

In order to increase the electrostatic control of the gate over the channel, the oxide thickness is reduced. However, the reduced oxide thickness leads to more tunneling and thereby increases the leakage current between gate and channel and consequently increases the static power consumption of the device [47]. One of the solutions to mitigate this problem is to use multiple gates as discussed earlier. Using high-к dielectric instead of Si02 can also be a solution. However, the high- k dielectric results in increased interface defects. Another solution is gate-oxide stack [48]. In this technique, a thick layer of high-к oxide is sandwiched with a thin layer of Si02. The thin layer of high-к oxide results in increased oxide thickness, thereby reducing tunneling/leakage current while at the same time providing more

Different configurations of gate-all-around MOSFET structure, (a) Squareshaped GAAorquad gate MOSFET. (b) Rectangular-shaped GAA MOSFET. (c) Cylindricalshaped GAA MOSFET

FIGURE 5.5 Different configurations of gate-all-around MOSFET structure, (a) Squareshaped GAAorquad gate MOSFET. (b) Rectangular-shaped GAA MOSFET. (c) Cylindricalshaped GAA MOSFET.

electrostatic control of the gate over the channel. The gate-oxide stack in multigate MOSFETs enhances the immunity against short channel effects, increases ON/OFF current ratio, increases intrinsic DC gain (Av), cutoff frequency (fT), and maximum oscillation frequency (fMAX) [49,50]. The technique however needs an extra fabrication step which makes it bit costlier.

Gate Metal Work Function Engineering

In order to increase the mobility of carriers in nanoscale MOSFETs, the channel is either lightly doped or undoped [51]. The doping of the channel controls the threshold voltage of the MOSFET and immunity to short channel effects. However, if undoped channel is used, controlling the threshold voltage is not possible. In that case, the gate material will control the threshold voltage of the device. When using the traditional polysilicon as the gate material in nanoscale MOSFET, it forms a depletion region with the high-к dielectric, thereby increasing the effective oxide thickness [52]. This problem can be avoided by using highly doped polysilicon gates. However, the highly doped polysilicon gates lead to negative threshold voltage in n-channel MOSFETs and positive threshold voltage in p-channel MOSFETs. These effects make polysilicon unsuitable as gate material for nanoscale MOSFET, which can be avoided by using metal gates. Metal gates are compatible with high-к dielectrics and provide more carrier mobility in the channel by reducing the transverse electric field [53,54]. Besides, nowadays the work function of the metal gate can be tuned to adjust the threshold voltage [55,56]. It has also been demonstrated that using multiple materials with different work function in gate leads to the enhanced mobility of the carriers in the channel and provides a screening effect to suppress short channel effects.

For example, if two metals of different work functions are used in gate with metal of higher work function placed on the source side and the metal with lower work function placed on the drain side, the mobility of the carriers in the channel enhances and a screening effect to suppress short channel effects is produced. This becomes possible due to the fact that using the work functions in the above manner results in higher threshold voltage towards source side and less threshold voltage towards drain side [57]. The same effect has been observed in multigate devices as well [58-63].

Channel Engineering

Traditionally, the doping of the channel is kept uniform and the whole channel is inverted by the gate potential. However, if the graded doping is considered instead of uniform doping, the region with less doping inverts first and thereby decreases the effective length of the device and hence increases the drive current of the device. For example, if the drain end of the channel is lightly doped or undoped and source side of the channel is heavily doped, the drain side of the channel will have lower threshold voltage and source side of the channel will have higher threshold voltage. As the gate potential is applied, the drain side of the channel becomes an extension of drain and thereby reduces the effective channel length and increases the drive current of the device. The low doping on the drain side also increases the mobility of carriers in the channel. Graded channel devices have improved punch-through and DIBL characteristics while at the same time enhancing the device reliability. Graded channel devices do not require complex fabrication processes and are fully compatible with mainstream CMOS technology [64,65].

Strained Layer

If a thin layer of a material is epitaxially grown on the thick substrate of the same material, no mismatch occurs and no dislocations are formed. However, if the lattice constant of the top thin layer is different from the substrate, the lattice constant of the top thin layer changes to match the thick substrate or the strain of the top layer takes place [66]. Depending upon whether the original lattice constant of the top thin layer was greater or less than the lattice constant of the substrate, compressive or tensile strain of the top layer takes place [67]. The maximum thickness (critical thickness) of the top strained layer depends on the difference in the original lattice constants of the top layer and substrate. If the thickness of top layer exceeds the critical thickness, strain is relieved and dislocations are formed. The strain leads to the change in energy levels and thereby energy gap. The strain usually lowers the effective mass of the holes and thereby increases the mobility of hole [68]. Therefore, strained layers are used in the channel of MOSFET to achieve higher mobility of carriers and higher drive current.

 
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