Performance Metrics of Resistive Random-Access Memory (RRAM)

Write Operation

In write operation, the important factors to be considered are the voltage amplitude (Vm) and the length of the write pulse (tn.r). In order to be compatible with the current VLSI technology, the range for voltage must be restricted within a few hundred millivolts and few volts. The smallest write voltage has been reported to be 0.6 V in a CBRAM cell [96]. As far as pulse widths are concerned, the desired length should be below 100 ns to compete with DRAM and win over flash. If the pulse widths for write operations are reduced below 10 ns, then RRAM has the chance to achieve the efficiency close to high-performance SRAM. Researchers have reported subnanosecond pulses capable of introducing resistive transitions adding to the possibility of RRAM replacing SRAM [31].

Read Operation

As in case of write operation, read operations are also characterized by the amplitude of the voltage required and length of pulse, but an additional constraint here is the requirement of a minimum read current (Ird). The read voltages (Vril) should be significantly smaller than Vwr in order to prevent any change of the resistance during the read operation. Because of constraints enforced by circuit design, Vrd cannot be less than approximately one-tenth of Vm. [96]. Taking into consideration the prowess of current sense amplifiers, the amount of lrd should be preferably larger than 1 pA to allow for fast detection. As far as pulse widths in read cycles are concerned, they should either be of the same duration as the write pulse or smaller. As far as RRAM is concerned, Vrd as small as 0.1 V has been already demonstrated [96].

Resistance Ratio

The ratio between the maximum achievable resistance to that of the minimum achievable resistance is known as resistance ratio. In practice, resistance ratios as small as 1.2—1.3 have been utilized in MR AM designs, but researchers suggest that in order to comply with the current design strategies, a ratio of greater than 10 would allow for small and very efficient sense amplifiers. Small and efficient sense amplifier designs would make RRAM cost-effective against flash memory. Resistance ratios are where RRAMs usually are far ahead of their counterparts, with ratios as high as 10s already reported [97].

Endurance

The maximum number of write cycles before a device starts to show performance deterioration is endurance. Traditional flash-based memory designs can usually have endurance rating between 103 and 107. In order to be competitive enough w'ith current flash designs, RRAM should provide the same endurance as flash or better. Current research trends and data collected over the years show that more than 1012 write cycles can be extrapolated from RRAM devices w'ith 1012 endurance cycles already demonstrated [96].

Retention

The maximum amount of time a device can retain its memory state after being programmed is a measure of retention. From a universal non-volatile memory point of view, the required retention time should be greater than 10 years while the device is kept under a thermal stress of up to 85°C and a constant stream of read pulses. Data and research over the years support the fact that RRAMs can retain data for a period greater than lOyears [96].

Uniformity

In RRAM cell, poor uniformity of various device characteristics is one of the significant factors limiting the manufacturing on a wider scale. The switching voltages, as well as both the HRS and the LRS resistances, are among the parameters exhibiting a high degree of variation. The variations of the resistance switching include temporal fluctuations (cycle-to-cycle) and spatial fluctuations (device-to-device). The stochastic nature of the formation and rupture of CF is believed to be the main reason for these variations. Cycle-to-cycle and device-to-device variability is a major hindrance for information storage in RRAM devices [98]. The observation of cycle- to-cycle variability is influenced by the change in the number of oxygen vacancy defects that arise in the CF due to its stochastic nature of formation and rupture during the switching event [99]. Due to this random nature of the CF, the prediction and the precise control of the shape of the CF becomes extremely challenging. This variability becomes worse as the compliance limit (i.e., compliance current “Icc”) is reduced. A lot of research has been conducted to improve the uniformity of RRAM, and several methods have been explored for the same. One of the methods utilizes the concept of inserting nanocrystal seeds w'hich confine the paths of the CF by enhancing the effect of local electric field [100]. In addition to the materials engineering approach, a novel programming method has also been suggested to reduce fluctuations. A multi-step forming technique was implemented in W/Hf02/Zr/TiN [101]-based RRAM to minimize the overshoot current due to the parasitic effects. A multi-step forming technique results in the gradual formation of the filament; thus, a low set/reset current is achieved improving the switching characteristics of the device. Various other methods such as constant voltage forming and hot forming (usually referred to as forming at a higher temperature) have also been investigated to effectively reduce the resistance variations [102]. Another method of achieving high uniformity is by applying a pulse train rather than a single pulse to a RRAM cell [103]. This approach not only results in improved uniformity but also enhances the multilevel capability of a RRAM cell.

Effect of Operating Temperature and Random Telegraph Noise

To achieve a reliable performance of the RRAM device, the effect of operating temperature and random telegraph noise (RTN) should be minimum. It is observed that the resistance of both the LRS and HRS states undergoes variations because of the change of operating temperature. The on-off resistance ratio (Ron/Roff) also decreases with an increase in temperature affecting the memory performance. RTN is another factor that affects the performance of RRAM. RTN decreases the memory margin between the HRS and LRS because of the extensive fluctuations in the read current during the read operation. Due to the effect of RTN, the read margin, scaling potential, and the multilevel cell capability of a RRAM cell are greatly affected [104]. The RTN is attributed to the trapping and de-trapping of electrons in the proximity of the CF in LRS, whereas it occurs in the tunneling gap in the HRS state. It is observed that with the decrease in operation current, the amplitude of RTN increases, thus highly affecting the HRS level. Therefore, it is necessary to ensure the additional resistance margin to achieve reliable performance.

 
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