Computer Organisation and Architecture: Evolutionary Concepts, Principles, and Designs


I. Fundamental Computer OrganisationComputer and Its EnvironmentHistory in ShortComputer Organisation and ArchitectureHardware and Software: An Introductory ConceptHardware and Software: Their Roles and CharacteristicsEvolution of Computers: Salient MilestonesThe Generation of Computers: Electronic EraVon Neumann Architecture: Stored-Program ConceptSecond-Generation Systems (1955–1965)Integrated Circuits (ICs) and Moore’s LawThird-Generation Systems (1965–1971): The MSI EraFourth-Generation Systems (1972–1978): The LSI EraFifth-Generation Systems (1978-1991): The VLSI EraSixth-Generation Systems (1991–Present): The ULSI EraGrand Challenges: Tomorrow’s MicroprocessorsEvolution of Operating System and System Software: Their RolesModern Operating SystemsGenesis of Computer Organisation and ArchitectureSummaryExercisesSuggested References and WebsitesComputer System OrganisationModular Design LevelsMethods of DesignThe Processor LevelDesign ApproachPerformance and Related FactorsProcessor ClockPerformance Assessment: A Rough EstimationDesign Principles: CISC and RISCSpeed-Up ApproachPerformance MeasurementsThe Register LevelCombinational ComponentsSequential ComponentsGeneral RepresentationCombinational CircuitsSequential CircuitsTri-State BuffersThe Gate LevelBasic Memory Components: Latches and Flip–FlopsGenesis of Digital SystemsSummaryExercisesSuggested References and WebsitesProcessor Basics – Structure and FunctionIntroductionProcessor (CPU) OrganisationFundamental ConceptsRegister OrganisationUser-Accessible RegistersControl and Status RegistersRegister Organisation in Microprocessor: IA-32/64 and MC68000Motorola MC68000 SeriesIntel IA-32 ArchitectureIntel IA-64 ArchitectureStack OrganisationGeneralized Structure of CPUCPU Operation: Instruction ExecutionInstruction SetMachine Instruction ElementsInstruction Formats and Design CriteriaTypes of OperandsIntel X-86 (IA-32 and IA-64) Data TypesTypes of Instructions and Related OperationsArithmeticLogicalShift OperationData TransferInput/Output (I/O)Transfer of ControlBranch Instructions Skip InstructionSubroutine Call InstructionSystem ControlSystem Call versus Subroutine CallOther Operations: IA-32 Instruction SetMMX (Multimedia Extension) OperationStreaming SIMD Extension (SSE)Instruction Addressing SchemeAddressing ModesIntel X-86 Addressing Modes: IA-32 and IA-64Register-Organised CPUAccumulator-Based CPU (Single Accumulator Organisation)General Register-Organised CPU (Multiple Register)The Intel IA-32/IA-64 ArchitectureRegister OrganisationStack-Organised CPU (A Stack Processor)Expression Evaluation and Reverse Polish NotationStack-Organised Symbolic LISP ProcessorSummaryExercisesSuggested ReferencesMemory OrganisationMemory System OverviewKey Characteristics of the Memory SystemThe Memory HierarchySemiconductor Main MemoryRandom-Access Memory (RAM)Cell OrganisationStatic RAM (SRAM)Dynamic RAM (DRAM)Schemes For Refreshing DRAMSRAM vs DRAM: A Rough ComparisonRAM OrganisationD Organisation½D (Word-Oriented) OrganisationAdvanced DRAM OrganisationSDRAMs (Synchronous DRAMs)DDR SDRAMRambus DRAM (RDRAM)Cache DRAM (CDRAM)Other Types of Random-Access Semiconductor MemoryROM (Read-Only Memory)PROM (Programmable ROM)EPROM (Erasable PROM)EEPROMs (Electrically Erasable PROM)Flash Memory (Flash EEPROM)USB Flash Drive: Pen DriveRAM Module OrganisationSerial-Access Memory: External MemoryCharacteristicsRotating Memory (Disk) OrganisationRead–Write MechanismDevice Controller: Rotating MemoryMagnetic DiskCommodity Disk ConsiderationsRAID: Redundant Array of Inexpensive DisksDisk CacheMagnetic TapeOptical Memory: External MemoryCompact Disk (CD) TechnologyCD-ROM (Compact Disk Read-Only Memory)CD-Recordable: CD-R (WORM)CD-Rewritable (CD-RW): Erasable Optical DiskDigital Versatile Disk (DVD)High-Definition Optical Disk: HD-DVD and Blu-RayVirtual MemoryBackgroundAddress SpaceAddress MappingTypes of Virtual MemoryAddress Translation MechanismsTranslation Lookaside Buffer (TLB)Working-Set ModelDemand Paging SystemsPage Replacement PrinciplesPage Replacement PoliciesNot Recently Used Page Replacement (NRU)First-In–First-Out (FIFO)Least Recently Used Page (LRU)Performance ComparisonSegmentationPure SegmentationSegmentation with PagingPaged Segmentation in Mainframe (IBM 370/XA)Paged Segmentation in Microprocessor (Intel Pentium)Cache MemoryBackgroundObjectiveHierarchical ViewPrinciplesCache–Main Memory Hierarchy: Its PerformanceCache DesignCache Design Issues: Different ElementsCache SizeBlock SizeMapping SchemesCache InitializationWriting into CacheReplacement Policy (Algorithm)Multiple-Level CachesUnified Cache and Split CacheImplementation: PENTIUM Cache OrganisationMotorola RISC MPC7450 Cache OrganisationCache AddressingPhysical Address CacheVirtual Address CacheMiss Rate and Miss PenaltyTypes of Cache Misses and Reduction TechniquesMiss Penalty and Reduction TechniquesCaches in MultiprocessorCache CoherenceReasons of Coherence ProblemCache Coherence Problem: Solution MethodologiesNo Private CacheSoftware SolutionHardware-Only SolutionTwo-Level Memory Performance: Cost ConsiderationMemory Hierarchy Design: Size and Cost ConsiderationInterleaved Memory OrganisationBackgroundMemory InterleavingTypes of InterleavingInterleaving in Motorola 68040ConclusionAssociative Memory OrganisationBackgroundImplementationWord-Organised Associative MemorySummaryExercisesSuggested References and WebsitesInput–Output OrganisationInput–Output SystemI/O Module: I/O InterfaceI/O Module DesignTypes of I/O Operations: Definitions and DifferencesProgrammed I/O (Using Buffer)Interrupt-Driven I/OInterrupt-Driven I/O: Design IssuesDirect Memory Access (DMA) I/OIntroductionDefinitionEssential FeaturesProcessing DetailsDifferent Transfer TypesImplementation Mechanisms: Different ApproachesI/O Processor (I/O Channels)IntroductionI/O ChannelI/O Processor (IOP) And Its OrganisationBus, Bus System and Bus DesignBus StructureBus ArbitrationBus ProtocolBus Design ParametersBus Interfacing: Tri-State DevicesSome Representative Bus Systems of Early DaysPCI (Peripheral Component Interconnect): Local BusSCSI (Small Computer System Interface) BUSUniversal Serial Bus (USB)FireWire Serial BusInfiniBandPORT and Its Different TypesSerial PortParallel PortUSB PortSummaryExercisesSuggested References and WebsitesControl Unit: Design and OperationIntroductionMicro-Operations: Fetch CycleDesign IssuesMethods of ImplementationHardwired ControlControl Unit LogicControl Signals in Accumulator-Based CPUMicroprogrammed ControlBasic Concepts: MicroinstructionsMicroprogrammed Control Unit OrganisationMicroinstruction Design IssuesHorizontal versus VerticalEncoding SchemesAddressing SchemesEmulationMerits and DrawbacksApplication AreasNanoprogrammingSummaryExercisesSuggested ReferencesArithmetic and Logic Unit OrganisationNumerical Representations: Number SystemsDecimal SystemBinary SystemHexadecimal and Octal SystemMerits of Hex and Octal SystemsBCD (Binary-Coded Decimal) CodeGray CodeNumber Representations: Binary SystemsSign-Magnitude Representation’s (One’s) Complement Representation’s (Two’s) Complement RepresentationConversion: Decimal to 2’s Complement and Vice VersaAddition and Subtraction: Signed NumbersOverflow: Integer ArithmeticCharactersArithmetic and Logic Unit (ALU)Fixed-Point ArithmeticAddition and SubtractionBasic AddersSubtractersHigh-Speed AdderCarry-Lookahead Adder (CLA)Adder ExpansionCarry-Save Adder (CSA)MultiplicationUnsigned IntegersSigned-Magnitude NumbersSigned-Operand MultiplicationFast Multiplication: Carry-Save AdditionDivisionUnsigned IntegersFloating-Point RepresentationNormalized FormRange and PrecisionIEEE Standard: Binary Floating-Point RepresentationExceptions and Special ValuesFloating-Point Representation: Merits and DrawbacksFloating-Point ArithmeticAddition and SubtractionImplementation: Floating-Point UnitMultiplication and DivisionImplementation: Floating-Point MultiplicationPrecision Considerations: Guard BitsTruncationRounding: IEEE StandardInfinity; NaNs; and Denormalized Numbers: IEEE StandardsSummary of Floating-Point NumbersSummaryExercisesSuggested References and WebsitesII. High-End Processor OrganisationPipeline ArchitecturePipeline ConceptPipeline Approach: Instruction-Level ParallelismImplementationLinear and Nonlinear (Static and Dynamic) PipelinesLinear Pipeline:Asynchronous and Synchronous ModelsCharacteristics and Behaviour: Space-TimeSpeed-Up, Efficiency and ThroughputNonlinear (Dynamic) PipelineReservation TableLatency and CollisionAreas of a PipelineInstruction PipelineLimitationsPipeline Hazards and Solution MethodologyStructural Hazard and Solution ApproachesData Hazard (Data Dependency) and Solution ApproachesControl HazardArithmetic PipelineAdder Pipeline DesignMultiplicatio Pipeline DesignPipeline Control and Collision-Free SchedulingControl Scheme: Collision VectorsState DiagramsGreedy Cycles and Minimum Average Latency (MAL)Dynamic Pipeline SchedulingImplementationSuperpipeline ArchitectureSuperpipeline PerformanceSuperscalar ArchitectureRequirements and Essential ComponentsMultipipeline SchedulingSuperscalar PerformanceSuperscalar Processors: Key FactorsImplementation: Superscalar ProcessorsSuperpipelined Superscalar ProcessorsSuperpipelined Superscalar PerformanceImplementation:Superpipelined Superscalar ProcessorsDEC Alpha 21X64Intel Pentium 4VLIW and EPIC ArchitecturesInstruction Bundles:the Intel IA-64 FamilyThread-Level Parallelism: MultithreadingScalar ProcessorSuperscalar ProcessorVLIW ProcessorSimultaneous Hardware Multithreaded Processor (SHMT)Chip Multiprocessors (Multicore Processors)Multicore ArchitectureBackgroundDefinitionDesign IssuesMulticore OrganisationBasic Multicore Implementation: Intel Core DuoIntel Core 2 DUOIntel Core 2 QuadMulticore with Hardware MultithreadingIBM Power 5Intel Core i7Distinctive Features of Intel Core i7 900-Series ProcessorsSun UltraSPARC T2 ProcessorSummaryExercisesSuggested References and WebsitesRISC ArchitectureBackground: Evolution of Computer ArchitectureCharacteristics of CICS and Its DrawbacksDrawbacksRISC: Definition and FeaturesRepresentative RISC ProcessorsRISC CharacteristicsThe RISC Impacts and DrawbacksDrawbacksRISC versus CISC DebateRunning Programs in High-Level LanguagesTechnology of the ComponentsRole of Large Register FileRISC Design Issues RISC Instruction SetRISC Instruction FormatRISC Addressing ModeRegister Windows: The Large Register FileRegister File and Cache MemoryComparison between RISCs and CISCsRISC PipeliningRISC and CISC Union: Hybrid ArchitectureTypes of RISC ProcessorsPowerPC ProcessorsSPARC Family of ProcessorsUltraSPARC ProcessorsMIPS ProcessorsPA-RISC ProcessorsARM (Advanced RISC Machine) ProcessorsMotorola Processors (MC 88000)Comparison of Four Representative RISC MachinesSummaryExercisesSuggested References and WebsitesParallel ArchitecturesIntroductionClassicfication of Computer Architectures: Flynn’s ProposalParallel Computers: Forms and IssuesParallel Computers: Its ClassificationParallel Computers: Its EnvironmentInterconnection NetworksInterconnection Network: Different TypesHierarchical Common (Shared) Bus SystemsCrossbar NetworksMultiport MemoryMultistage NetworksOmega Network (Perfect Shuffle)Benes NetworkThe Hot-Spot ProblemButterfly NetworkImplementation of Multistage NetworksComparison of Dynamic NetworksStatic Connection Networks (Message-Passing Approach)HypercubesMesh and TorusSystolic ArraysRingTree and StarFat TreeTransputerComparison of Static NetworksHybrid (Mixed Topology) NetworksImportant Characteristics of a NetworkMultiprocessor ArchitecturesShared-Memory MultiprocessorSymmetric Multiprocessors (SMP): UMA ModelDistributed Shared Memory Multiprocessors (DSM): NUMA ModelCache-Coherent NUMA: CC-NUMA ModelNo Remote Memory Access (NORMA)General-Purpose MultiprocessorsImplementation: A Mainframe SMP (IBM z990 Series)Operating System ConsiderationsMulticomputer ArchitecturesDesign ConsiderationsMulticomputer GenerationsDifferent Models of Multicomputer SystemsMultitiered Architecture: Three–tier Client–Server ArchitectureComputer NetworksDistributed SystemsClusters: A Distributed Computer System DesignDistinct AdvantageClassification of ClustersDifferent Clustering MethodsGeneral ArchitecturesOperating System ConsiderationsWindows ClusterSun ClusterBlade ServersSIMD MachinesSIMD Computer OrganisationsVector Processors and SIMD Vector ComputersVector StrideVector FittingVector Instruction FormatVector Instruction: Different TypesVector ProcessingVectorization InhibitorVectorizing CompilersDifferent Types of Vector Processor OrganisationsSalient Features of Vector OperationsBasic Vector Processor ArchitectureMemory-Access SchemesImplementation: The CRAY 1 ArchitectureArray Processors and SIMD Parallel ComputersApplicationsImplementation: Connection Machine CM 2 ArchitectureVector Processor Versus Array Processor: A Rough ComparisonMassively Parallel Processing (MPP) SystemRepresentative MPP System: Connection Machine CM-5Scalable Parallel Computer ArchitectureSupercomputersThe Contemporary Fastest Supercomputer SystemSummaryExercisesSuggested References and WebsitesAdditional ReadingSuggested Websites
 
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