Types of Operands

Various operations in machine instructions are executed on different types of data. Usually, the type of a unit of data to be used is determined by the operation to be performed on it. The most important general categories of data used as operand are as follows:

i. Numbers;

ii. Characters;

iii. Logical data;

iv. Addresses;

v. String.

Apart from the above-mentioned data types, some machines also support dedicated specialized data types or data structures used for special types of operations.

Numbers are used as operands in all machine languages, and most computers commonly use three types of numerical data, namely (i) integer or fixed point, (ii) floating point, and (iii) decimal, represented in binary form (machine's internal form) in the defined instruction formats. Character-type operands contain textual data or strings of characters that need some form of internal representation using a variety of suitable codes (ASCII, EBCDIC, BCD, etc.) within the machine in the form of a sequence of fixed number of bits. Each character in this code is represented by a byte (8 bits) in which a unique pattern of 7 bits, i.e. a total of 27 = 128 different characters comprising numeric characters (0-9), alphabetic characters (A-Z, and a-z),other special characters (+, *, &, @, etc.),and also some of the patterns of these 128 different types, are used to represent control characters for print control, communication procedures, and similar other purposes. The eighth bit in an 8-bit pattern of character representation is used as a parity bit for error detection or for other purposes. Logical data is a single unit of data, whether of numeric type or of character type, and is basically a set of bits. Various logical operations can be performed for manipulating individual bits (a word or other addressable unit) of such data, often referred to as bit twiddling. Addresses are unsigned data also used as operand in an instruction that do not participate directly in the operation indicated in the instruction; rather, it points to the location (i.e. indicating the address) where the actual value of the operand can be obtained. In many cases, some extra calculations must be computed to determine the actual address (location). Some machines even use different types of opcodes to indicate the operand as containing an address, and not data to be used directly in the operation. String is a set of characters of variable lengths used in many applications. Successive byte locations contain successive characters of the string. The beginning of the string is indicated by giving the address of the byte containing its first character. There are usually two ways to indicate the length (or end) of the string. A special control character representing the meaning "end of string" can be used as the last character in the string to signify the end of the string, or a separate memory word location or a processor register can be employed, which contains a number that indicates the length of the string in bytes.

Intel X-86 (IA-32 and IA-64) Data Types

Intel X-86 processors deal with numerous data types of different lengths as addressable units, such as 8 (bytes), 16 (word), 32 (doubleword), 64 (quadword), and 128 (double quad- word) bits in length using ASCII codes. All X-86 processors of Intel while storing data in memory always use the little-endian (for more details about endianness, see Chapter 4) convention of byte numbering in memory. Moreover, at the time of storing data of any type, of any length unit, there is no need to maintain the respective boundary alignments (i.e. storing of words does not require any alignment at even-numbered addresses; double- words need not be aligned at addresses evenly divisible by 4, and so on), which eventually facilitates efficient memory utilization and offers tremendous flexibility in organizing data structures. Apart from the general data types of different lengths as described earlier, the X-86 also provides an impressive array of specific data types that are identified and operated on by some particular instructions.

The numerical data types supported by X-86 for signed integers are represented in two's complement representations (see Chapter 7) and may be 16,32, or 64 bits long. The floatingpoint data type, however, refers to a variety of types with different ranges of precision (see Chapter 7). All the numerical data types used in IA-32 and IA-64, however, conform to IEEE 754 standards. The characters used here are usually letters of the alphabet, decimal digits, punctuation marks, and so on, apart from other types of characters known as special characters and control characters used for specific purposes. The later versions of the Pentium line of processors virtually provide SIMD (see Chapter 10) operations especially for MMX applications using packed SIMD data types, a derived data types in which multiple operands are packed into a single-referenced memory item, and these multiple operands within an item are then executed in parallel by a single instruction that eventually gives a flavour of SIMD operations. Some of the commonly used packed data types of this form are as follows:

  • Packed byte and packed byte integer: 8-bit bytes are packed into a 64-bit quad- word or 128-bit double quadword, interpreted as a bit field or as an integer.
  • Packed word and packed word integer: 16-bit words are packed into a 64-bit quadword or 128-bit double quadword, interpreted as a bit field or as an integer.
  • Packed doubleword and packed doubleword integer: 32-bit doublewords are packed into a 64-bit quadword or 128-bit double quadword, interpreted as a bit field or as an integer.
  • Packed quadword and packed quadword integer: Two 64-bit quadwords are packed into a 128-bit double quadword, interpreted as a bit field or as an integer.
  • Packed single-precision floatingpoint and packed double-precision floatingpoint: Four 32-bit floating-point or two 64-bit floating-point values are packed into a 128-bit double quadword, interpreted as a floating-point number.

Types of Instructions and Related Operations

Each instruction in the instruction set specifies some operation indicated by the opcode, included as one of the fields in the instruction. The number of different types of operations (expressed by opcodes) available in a machine varies widely from machine to machine, and this is considered as one of the important criteria of a machine design decision. However, we concentrate here only on some general types of operations that are found on almost all machines. The different types of commonly used operations that most CPUs perform can be typically categorized as:

i. Arithmetic;

ii. Logical;

iii. Shift operation;

iv. Data transfer;

v. I/O;

vi. Conversion;

vii. Transfer of control;

viii. System control.

Arithmetic

Basic arithmetic operations such as add, subtract, multiply, and divide are ALU functions; are mainly provided with operands having signed/unsigned integer (fixed-point) numbers, floating-point data, binary data, or decimal data; and are often applicable to single-precision, double-precision, or extended-precision data for floating-point numbers.

In case of accumulator-type organisation, an arithmetic addition may be defined as ADD X, where X is the address of the operand. The ADD instruction, in this case, results in the implicit accumulator operation, like AC AC + M [X], where M [X] is the content of memory word located at address X. This is an example of one-operand instruction.

In case of general register-type organisation, an arithmetic addition may be defined as ADD Rl, R2; this actually denotes the operation: R1 R1 + R2; here, the destination operand (register Rl) is the same as one of the source operands (register Rl). This is an example of two-operand instruction. The same instruction can be written in another form using different source operands and destination operand like ADD Rl, R2, R3; this denotes the operation Rl R2 + R3. This is an example of three-operand instruction.

In case of stack-organised CPU, an arithmetic addition may be simply defined as ADD. In stack-organised computers, operation-type instruction needs no address field, because here the operation is performed on the implicit two operands that are the top two elements of the stack. These two top elements will be popped off the stack: the addition operation will be performed and the sum will then be pushed into the TOS. All the operands are implied to be in the stack. This is an example of zero-operand instruction.

In addition to the usual arithmetic instructions for signed integer numbers, Intel IA-32 architecture incorporates instructions for integer multiply and divide, as well as instructions for operations on floating-point numbers.

For details, see the website: http://routledge.com/9780367255732.

Logical

Most of the machines have a variety of operations for manipulating individual bits of data (a byte, a word, or other addressable unit). These operations, known as logical operations, are based upon Boolean operations. Some of these operations listed below can be performed on Boolean or binary data.

A

В

NOT A

NOT В

A AND В

A OR В

AXORB

A = В

0

0

1

1

0

0

0

1

0

1

1

0

0

1

1

0

1

0

0

1

0

1

1

0

1

1

0

0

1

1

0

1

Similar to arithmetic operations, all types of logical operations may also include data transfer operations before the actual action of ALU begins.

Some typical and most commonly used logical and bit-manipulation instructions are given in the website: http://routledge.com/9780367255732.

Shift Operation

In addition to bit-wise logical operations, most machines offer a variety of shifting and rotating functions. With a logical shift, the bits of a word are shifted left or right. Whatever be the type of shift, on the one end the bit shifted out is lost, and on the other end a 0 is injected in for padding. Logical shift can be primarily used for isolating fields within a word. The Os that are injected into a word displace undesirable information which is shifted out at the other end. The operation codes SHL and SHR are normally used to indicate logical shift-left and shift-right operations, respectively. Figure 3.5 illustrates such logical-shift operations for a better understanding.

The arithmetic shift operation treats the data as a signed integer, shifts the data to the left or right, and does not shift the sign bit. On an arithmetic right-shift (operation code SHRA),it is necessary that the sign bit in the leftmost position remains unchanged and the sign bit is normally replicated into the bit position to its right as depicted in Figure 3.6. With numbers represented in 2's complement notation, an arithmetic left-shift (operation code SHLA) or SHRA corresponds to multiplication or division by 2, respectively, provided there would be no occurrence of an overflow or underflow situation. The large IBM S/390 system provides this instruction, but many processors, such as Intel Itanium and IBM PowerPC, do not include this instruction.

The circular (rotate) shift preserves all of the bits being operated on. It circulates the bits stored in the register around the two ends without the loss of information, as shown

FIGURE 3.5

Logical shift operation, (a) Logical left shift and (b) logical right shift.

FIGURE 3.6

Arithmetic shift operation, (a) Arithmetic left shift and (b) arithmetic right shift.

FIGURE 3.7

Rotate (circular) shift operation, (a) Left rotate and (b) right rotate.

in Figure 3.7. This is accomplished by connecting the serial output of the shift register to its serial input. Many useful actions employ the shift rotate operation (ROR for rotate right, and ROL for rotate left) as a part of their activities.

Similar to the arithmetic operation, all types of shift operations may involve data transfer operations before the commencement of actual ALU operation. Many machines have different types of the most commonly-used shift operations and their corresponding instructions. However, mnemonic names may differ on different machines for the same type of instructions.

A list of a few of these operations with examples is given in the website: http://routledge. com/9780367255732.

 
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