Representative RISC Processors

Generic RISC processors are called the scalar RISC processors since they are designed to issue one instruction per cycle. The first RISC machine in 1974 was an experimental project IBM/801 ECL, which was further enhanced by IBM in 1986 as PC/RT processor, and later, IBM released the RISC System RS/6000 line of computers in 1990 using POWER architecture. A group of Berkeley scientists led by David Patterson in 1980 designed RISC I and then RISC II within a short period. In 1981, John Hennessy at Stanford designed and fabricated a somewhat different RISC chip named the MIPS (Microprocessor without Interlocking Pipe Stages), and formed a company that introduced MIPS RX000 series with the first member MIPS R2000 and subsequently, MIPS R3000, MIPS R4000 (1991), and finally MIPS R10000 (1994). In 1987, SUN Microsystems developed an open microprocessor design SPARC (Scalable Processor ARChitecture), architecture, and not a chip. About half a dozen semiconductor vendors, such as Fujitsu, Cypress, LSI Logic Inc. and Texas Instruments, have been given licence to produce SPARC chips using different technologies (CMOS, ECL, GaAs (gallium arsenide), gate array, VLSI, etc.). A GaAs SPARC was reported to yield a 200-MIPS peak at 200-MHz clock rate. In 1988, Motorola launched RISC 88000, and in 1990, Motorola launched M88100. From 1993 onwards, Motorola implemented their 7XX and 7XXX lines of processors in the line of PowerPC processors (6XX lines, such as 601, 603, 604, etc.), with MPC prefix on their labelling. They introduced one of the latest versions of the processor in the MPC7XXX line, the MPC7450. In 1989, Hewlett-Packard (HP) announced their РА-RISC with a version PA-RISC 1.1 (1990), and then changed the design significantly to release PA-RISC 2.0 (1996) with 64-bit extensions. In 1989, Intel released its i860 using VLIW architecture, and later Intel 80960 microprocessor, a member of the i960 family of pipelined 32-bit RISCs. In 2993, Apple, IBM, and Motorola jointly developed single-chip microprocessor: the PowerPC; the first member was the PowerPC 601 processor. This family, however, included the 603, 604, 620, and the other models of the 6XX line, which shared a common architecture. In 2992, DEC introduced the Alpha architecture and later was acquired by Compaq, and Alpha processors have since then been labelled with the numbering sequence 21X64, having X = 0,1, and 2. Advanced micro device (AMD) has imbibed RISC culture and launched AMD 29000 (1990) using floating-point unit (FPU) outside the CPU chip (off-chip) like SPARC.

In the early 1980s, ARM Limited, evolved out of Acorn Computers, Inc. has designed a family of microprocessors which were mainly low-powered and low-cost ones, and were mostly targeted for applications in the domain of embedded systems, such as mobile telephones, communication modems, portable digital fault-detection accessories, and for similar other pieces of equipment. The ARM designs are usually integrated with application-specific hardware on the same chip. That is why, the companies engaged in manufacturing embedded systems and customized application-specific products can incorporate the designs of ARM processor into their products under licence from ARM Limited. This company later collaborated with DEC (later, in the folds of the Compaq Company) to produce Strong ARMCPU. The ARM SA-110 CPU, however, is now manufactured by Intel.

RISC Characteristics

The major attributes of RISC that have been defined most recently are as follows:

  • • Simple instruction set consisting of relatively few instruction types and only some addressing modes;
  • • Fixed and easily decoded instruction formats;
  • • Fast single-cycle instruction execution;
  • Hardwired rather than microprogrammed control;
  • • Limited memory access, mainly, confined to load and store instructions;
  • • Large number of registers, to minimize very often interactions with memory;
  • • Massive pipelining, a key to speed up RISC machines;
  • • Use of optimizing compilers to yield enhanced performance of the resulting object code.

In fact, several of these RISC attributes are closely interrelated. The major thrust to achieve desired level of performance is, however, entrusted on compilation process that requires the machine architects and compiler writers to cooperate closely in the design process.

The RISC Impacts and Drawbacks

RISC processor has several advantages due to some of its inherent characteristics that provide attractive outcomes than its CISC counterpart. Incidentally, some of these advantageseventually culminate to also create its several drawbacks as experienced by the designersas well as by the users. A few of all these are as follows: • Simple instruction set with reduced complexity provides higher clock rate and alower CPI, providing higher MIPS ratings;

• Use fewer transistors, even considering large register files makes the design easierand simpler with perhaps lesser bugs than usually found in microcode in CISC;}} [1]

  • • Availability of enough space within the die (chip) facilitates to include several extra functionalities, such as memory management unit (MMU) and floatingpoint arithmetic units, on the same chip;
  • • High-level language compiler produces more efficient codes (microinstructions) which are then directly executed by the underlying hardware, with no intervening interpreter (microprogram);
  • • Loading of instructions in a RISC processor is simple and decoding is simplified as opcodes and address fields are located in the same positions for all instructions;
  • • As RISC is simpler than corresponding CISC, a new RISC processor can be designed, developed, and tested more quickly that summarily reduces the time between design and shipment - a crucial issue in a rapidly moving and competitive industry.


  • • The CISC architecture is so compatible that it is identical from micro (PC) to mainframe, thereby offering a complete range of the family of machines. The smaller models can even be microprogrammed to achieve their functionality in software (microcode), while the larger models can be hardwired for gaining speed. This marvellous concept is not found in RISC architecture;
  • • A RISC processor suffers from the absence of some useful sophisticated instructions that are mostly available in contemporary CISC;
  • • The presence of hardwired control appears to be a two-edged sword. On the one hand, it expedites the speed of the execution, and on the other hand, it is considered as another shortcoming of RISC since it is less flexible and more error-prone;
  • • Increase in RISC program length results in more instruction traffic and larger size of memory demand that might create reasons to drop RISC from favour;
  • • Use of a large register file is another concern causing problems in RISC. Although a larger register set can hold more intermediate results and reduce the to-and-fro data traffic between the faster CPU and slower memory, the register decoding system itself becomes more complicated.
  • • In fact, it is really difficult to determine the optimal sizes of register set, I-cache, and D-cache, which are directly related to the performance of the RISC.

RISC versus CISC Debate

The debate between RISC and CISC designers has lasted for more than a decade. The RISC camp began to claim that CISC had reached a dead end and should be abandoned. The designers and associates of CISC have taken a close and critical look at RISC technology, and found problems that the RISC proponents have tried to sweep under the rug. To enter the heart of the RISC-CISC controversy, we present here the arguments offered by both sides, to let the readers form their own views, draw their own conclusions, and make an informed judgement of their own.

Running Programs in High-Level Languages

  • • The benchmarking between RISC and CISC with regard to the performance of high-level language program execution reveals that procedure calls are better handled by RISC than by CISC, but jumps in a program (GO TO) are handled better by CISC;
  • • RISC outperforms CISC in case of recursive programs, but is rudimentary (primitive) in I/O handling and hence is far behind CISC;
  • • CISC outclasses RISC with regard to floating-point calculation and even in integer multiplication and division with all three varieties: single (32-bit), double (64-bit), and extended (128-bit) precision;
  • • Better design of compiler in RISC does a great job with better use of registers and factored out CISC in executing users' job;
  • • CISC machines while running on versatile operating system (like VMS in VAX) clearly elbowed out RISC. But how this superior performance of CISC could be then considered, being the credit of only of its underlying architecture.

Hence, the set of programs being run for benchmarking plays an important role in declaring which one is faster. Thus, an artificially designed synthetic benchmark program could be used for this purpose, which typically does no I/O at all, and really tests the compiler and CPU performance. Such a synthetic benchmark that measures floating-point performance in whetstones (a statistically average floating-point instructions) per second, and later in dhrystones (measured only integer computations), can give at least a rough measure to compare RISC and CISC machine performances, accepting the factors such as compiler quality, register allocation, cache performance, etc. which can affect the end result.

A pilot test with four RISC chips from four vendors when executed based on this idea has surprisingly outperformed the IBM's top-of-the-line 3090/200 mainframe (CISC). Hence, it becomes hard to deny that RISC machines are really very fast.

Technology of the Components

The inherent technology on which these two categories of machines have been built is also an important factor in this comparison. RISC used ECL transistors that switch much faster than CMOS transistors used in CISC. These two machines used different clock rates; different buses; different types of memory chips, including caches; different MMU; different pipelining techniques etc.

Technology-independent measure is also not a full proof as it first appears. Pre-fetching of instructions often adds extra bus load that may have an impact on the overall performance.

Role of Large Register File

The execution of simulated programs on different types of register model, such as

  • • Overlapping register windows (large VAX: CISC and SPARC: RISC),
  • • Non-overlapping register windows, and
  • • A single set of registers, reveals that overlapping register windows offer much faster operation, but for recursive programs, they actually slow down. The conclusion is that overlapping register windows are a good idea, but this tells very little about RISC architecture versus CISC architecture.

The comparison of an overlapping register as in CISC (VAX) with an overlapping register used in RISC is not fair, because CISC would take up much more chip area than the RISC. Put in other words, if a RISC designer were given the same amount of chiparea that CISC machine enjoys, he/she could either include a much larger register file, an on-chip memory cache, or other features that could yield even better performance.

However, the boundary between RISC and CISC architectures has gradually faded away, because both are now implemented with the same hardware technology. For example, the Motorola 88100, Intel Pentium, and VAX 9000 are built with a mix of some useful features taken from both the RISC and CISC camps.

It can be judiciously concluded that it is the applications that will ultimately decide and determine the best choice of a processor architecture. It can be convincingly predicted that the evolving architecture of tomorrow's processor might even be a hybrid, taking some of the positive features from both the tenets.

  • [1] Use of relatively few transistors occupies very little space than conventional CISCusing silicon chips and is thus well suited to make use of very-high-speed chipsbased on GaAs instead of silicon;
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