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Home arrow Computer Science arrow Hardware Security and Trust: Design and Deployment of Integrated Circuits in a Threatened Environment


In this chapter, we tried to give a rigorous overview on the PUF research field, with particular attention to existing architectures and adopted quality metrics. Indeed, as PUF is a concept which has been formed during time, we gave a collection of functional aspects with a formal notation. On the pragmatic level, we included in the chapter an exhaustive list of proposed PUF architectures in the literature, illustrating their strong points and main characteristics. Moreover, we briefly reported some attacks against PUFs, covering all categories of attacks.


  • 1. Amelino D, Barbareschi M, Battista E, Mazzeo A. How to manage keys and reconfiguration in WSNs exploiting sram based PUFs. In: Intelligent interactive multimedia systems and services 2016. Springer International Publishing; 2016. p. 109-19.
  • 2. Anderson JH. A PUF design for secure FPGA-based embedded systems. In: Proceedings of the 2010 Asia and South Pacific design automation conference. IEEE Press; 2010. p. 1-6.
  • 3. Barbareschi M, Bagnasco P, Mazzeo A. Authenticating IOT devices with physically unclonable functions models. In: 2015 10th international conference on P2P, parallel, grid, cloud and internet computing (3PGCIC). IEEE; 2015. p. 563-7.
  • 4. Barbareschi M, Battista E, Mazzeo A, Mazzocca N. Testing 90 nm microcontroller SRAM PUF quality. In: 2015 10th international conference on Design and Technology of Integrated Systems in Nanoscale Era (DTIS). IEEE; 2015. p. 1-6.
  • 5. CheriZ, Danger J-L, Guilley S, Bossuet L. An easy-to-design PUF based on a single oscillator: the loop PUF. In: 2012 15th euromicro conference on Digital System Design (DSD). IEEE; 2012. p. 156-62.
  • 6. Cilardo A. Efficient bit-parallel GF(2m) multiplier for a large class of irreducible pentanomials. IEEE Trans Comput. 2009;58(7):1001-8.
  • 7. Cilardo A. New techniques and tools for application-dependent testing of FPGA-based components. IEEE Trans Ind Inform. 2015;11(1):94-103.
  • 8. Cilardo A, Barbareschi M, Mazzeo A. Secure distribution infrastructure for hardware digital contents. IET Comput Digit Tech. 2014;8(6):300-10.
  • 9. Cilardo A, Mazzocca N. Exploiting vulnerabilities in cryptographic hash functions based on reconfigurable hardware. IEEE Trans Inform Forensics Secur. 2013;8(5):810-20.
  • 10. Cortez M, Dargar A, Hamdioui S, Schrijen G-J. Modeling sram start-up behavior for physical unclonable functions. In: 2012 IEEE international symposium on defect and fault tolerance in VLSI and nanotechnology systems (DFT). IEEE; 2012. p. 1-6.
  • 11. Dai J, Wang L. A study of side-channel effects in reliability-enhancing techniques. In: DFT’09. 24th IEEE international symposium on defect and fault tolerance in VLSI systems, 2009. IEEE;
  • 2009. p. 236-44.
  • 12. Dodis Y, Reyzin L, Smith A. Fuzzy extractors: how to generate strong keys from biometrics and other noisy data. In: Advances in cryptology-eurocrypt 2004. Springer; 2004. p. 523-40.
  • 13. Feiten L, Spilla A, Sauer M, Schubert T, Becker B. Analysis of ring oscillator PUFs on 60 nm FPGAs. In: European cooperation in science and technology.
  • 14. Gassend B, Clarke D, Van Dijk M, Devadas S. Silicon physical random functions. In: Proceedings of the 9th ACM conference on computer and communications security. ACM; 2002. p. 148-60.
  • 15. Guajardo J, Kumar SS, Schrijen G-J, Tuyls P. Physical unclonable functions and public-key crypto for FPGA ip protection. In: International conference on field programmable logic and applications, 2007. FPL 2007. IEEE; 2007. p. 189-95.
  • 16. Hori Y, Yoshida T, Katashita T, Satoh A. Quantitative and statistical performance evaluation of arbiter physical unclonable functions on FPGAs. In: 2010 international conference on reconfigurable computing and FPGAs (ReConFig). IEEE; 2010. p. 298-303.
  • 17. Hospodar G, Maes R, Verbauwhede I. Machine learning attacks on 65 nm arbiter PUFs: accurate modeling poses strict bounds on usability. In: 2012 IEEE international Workshop on Information Forensics and Security (WIFS). IEEE; 2012. p. 37-42.
  • 18. Huang M, Li S. A delay-based PuF design using multiplexers on FPGA. In: 2013 IEEE 21st annual international symposium on Field-Programmable Custom Computing Machines (FCCM). IEEE; 2013. p. 226.
  • 19. Kocher P, Jaffe J, Jun B. Differential power analysis. In: Advances in CryptologyCRYPTO99. Springer; 1999. p. 388-97.
  • 20. Kocher PC. Timing attacks on implementations of Diffie-Hellman, RSA, DSS, and other systems. In: Advances in CryptologyCRYPTO96. Springer; 1996. p. 104-13.
  • 21. Kong J, Koushanfar F, PendyalaPK, Sadeghi A-R, WachsmannC. PUFatt: embedded platform attestation based on novel processor-based PUFs. In: 2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC). IEEE; 2014. p. 1-6.
  • 22. Kumar SS, Guajardo J, Maes R, Schrijen G-J, Tuyls P. The butterfly PUF protecting ip on every FPGA. In: IEEE international workshop on hardware-oriented security and trust, 2008. HOST 2008. IEEE; 2008. p. 67-70.
  • 23. Layman PA, Chaudhry S, Norman JG, Thomson JR. Electronic fingerprinting of semiconductor integrated circuits, May 18 2004. US Patent 6,738,294.
  • 24. Lee JW, Lim D, Gassend B, Suh GE, Van Dijk M, Devadas S. A technique to build a secret key in integrated circuits for identification and authentication applications. In: 2004 symposium on VLSI circuits, 2004. Digest of technical papers. IEEE; 2004. p. 176-9.
  • 25. Lim D, Lee JW, Gassend B, Suh GE, Van Dijk M, Devadas S. Extracting secret keys from integrated circuits. IEEE Trans Very Large Scale Integr VLSI Syst. 2005;13(10):1200-5.
  • 26. Linnartz J-P, Tuyls P. New shielding functions to enhance privacy and prevent misuse of biometric templates. In: Audio-and video-based biometric person authentication. Springer; 2003. p. 393-402.
  • 27. Maes R, Tuyls P, Verbauwhede I. Intrinsic PUFs from flip-flops on reconfigurable devices. In: 3rd Benelux workshop on information and system security (WISSec 2008), vol. 17; 2008.
  • 28. Maes R, Tuyls P, Verbauwhede I. Low-overhead implementation of a soft decision helper data algorithm for SRAM PUFs. In: Cryptographic hardware and embedded systems-CHES 2009. Springer; 2009. p. 332-47.
  • 29. Maes R, Verbauwhede I. Physically unclonable functions: a study on the state of the art and future research directions. In: Towards hardware-intrinsic security. Springer; 2010. p. 3-37.
  • 30. Maiti A, Casarona J, McHale L, Schaumont P. A large scale characterization of RO-PUF. In: 2010 IEEE international symposium on Hardware-Oriented Security and Trust (HOST). IEEE;
  • 2010. p. 94-9.
  • 31. Maiti A, Schaumont P. Improved ring oscillator PUF: an FPGA-friendly secure primitive. J Cryptol. 2011;24(2):375-97.
  • 32. Majzoobi M, Koushanfar F, Potkonjak M. Testing techniques for hardware security. In: IEEE international test conference, 2008. ITC 2008. IEEE; 2008. p. 1-10.
  • 33. Merli D, Schuster D, Stumpf F, Sigl G. Semi-invasive em attack on FPGA ro PUFs and countermeasures. In: Proceedings of the workshop on embedded systems security. ACM; 2011.

p. 2.

  • 34. Merli D, Schuster D, Stumpf F, Sigl G. Side-channel analysis of PUFs and fuzzy extractors. In: Trust and trustworthy computing. Springer; 2011. p. 33-47.
  • 35. Merli D, Stumpf F, Eckert C. Improving the quality of ring oscillator PUFs on FPGAs. In: Proceedings of the 5th workshop on embedded systems security. ACM; 2010. p. 9.
  • 36. Naccache D, Fremanteau P. Unforgeable identification device, identification device reader and method of identification, July 18 1995. US Patent 5,434,917.
  • 37. Rampon J, Perillat R, Torres L, Benoit P, Di Natale G, Barbareschi M. Digital right management for IP protection. In: 2015 IEEE computer society annual symposium on VLSI (ISVLSI). IEEE; 2015. p. 200-3.
  • 38. Ruhrmair U, Sehnke F, Solter J, Dror G, Devadas S, Schmidhuber J. Modeling attacks on physical unclonable functions. In: Proceedings of the 17th ACM conference on computer and communications security. ACM; 2010. p. 237-49.
  • 39. Schrijen G-J, van der Leest V. Comparative analysis of SRAM memories used as PUF primitives. In: Design, Automation Test in Europe conference exhibition (DATE); 2012. p. 1319-24.
  • 40. Selimis G, Konijnenburg M, Ashouei M, Huisken J, De Groot H, Van der Leest V, Schrijen G-J, Van Hulst M, Tuyl P. Evaluation of 90 nm 6T-SRAM as physical unclonable function for secure key generation in wireless sensor nodes. In: 2011 IEEE International Symposium on Circuits and Systems (ISCAS). IEEE; 2011. p. 567-70.
  • 41. Suh GE, Devadas S. Physical unclonable functions for device authentication and secret key generation. In: Proceedings of the 44th annual design automation conference. ACM; 2007. p. 9-14.
  • 42. Tolk KM. Reflective particle technology for identification of critical components. Technical report, Sandia National Labs., Albuquerque, NM (United States); 1992.
  • 43. Vatajelu EI, Natale GD, Barbareschi M, Torres L, Indaco M, Prinetto P. STT-MRAM-based PUF architecture exploiting magnetic tunnel junction fabrication-induced variability. J. Emerg. Technol. Comput. Syst. 2016;13(1):5:1-5:21.
  • 44. Wild A, Guneysu T. Enabling SRAM-PUFs on xilinx FPGAs. In: 2014 24th international conference on Field Programmable Logic and Applications (FPL). IEEE; 2014. p. 1-4.
  • 45. Yin CED, Qu G. LISA: maximizing RO PUF’s secret extraction. In: 2010 IEEE international symposium on Hardware-Oriented Security and Trust (HOST). IEEE; 2010. p. 100-5.
  • 46. Yin C-E, Qu G. Improving PUF security with regression-based distiller. In: Proceedings of the 50th annual design automation conference. ACM; 2013. p. 184.
  • 47. Yu M-D, Sowell R, Singh A, M’Raihi D, Devadas S. Performance metrics and empirical results of a PUF cryptographic key generation ASIC. In: 2012 IEEE international symposium on Hardware-Oriented Security and Trust (HOST). IEEE; 2012. p. 108-15.
  • 48. Yu MDM, Devadas S. Recombination of physical unclonable functions; 2010.
  • 49. Zhang J, Wu Q, Lyu Y, Zhou Q, Cai Y, Lin Y, Qu G. Design and implementation of a delay- based PUF for FPGA IP protection. In: 2013 international conference on Computer-Aided Design and Computer Graphics (CAD/Graphics). IEEE; 2013. p. 107-14.
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