Defining the LUT Placement

One LCELL is always synthesised in one logic element (LE) (cf. Fig. 11.6). The Quartos compiler in normal operation places the LEs as it deems best according to timing and power supply considerations. This, however, can lead to the delay of one wire being smaller than that of another wire on all devices. For good uniqueness properties of delay-based PUFs it is necessary that the delays between sampled components (e.g. ROs) are as homogeneous as possible. To fine-tune a delay-based PUF, it is necessary to take control of this placement; at least for the relevant PUF components. This can be achieved in the following two ways, both of which are suited for different scenarios. Method 1 is practical for large-scale customisations of many LCELLs at once. However, a greater one-time effort is necessary to write a script producing the required file entries. Method 2 is practical for punctual customisations via graphical user interface but therefore very arduous for large amounts of LCELLs.

Method 1: Customising the Quartus Settings File

One way to define the placement is by custom entries in the Quartus Settings File. A great advantage of this method is that it can be achieved with the free Quartus Web Edition. It is most practical, when a script is used to generate the custom entries automatically. The Quartus Settings File with the .qsf extension is found in the Quartus project’s root directory. Here, the location of each individual LCELL can be defined. To do so, the “Full Name” of the “Node” must be known by which the respective LCELL is identified in Quartus. It can be found under “Node Properties” in the Quartus Chip Planner when clicking on the LE of an LCELL. In the case of our running example, those “Full Names” would be, e.g.

for the second and third LCELL of RO 9, and so forth. Notice, that myPUF corresponds to the name of the Quartus project as ros and ro correspond to the VHDL entities described in Listings 11.1 and 11.2. The identifiers ro_gen and ro_i are the ones used in the GENERATE command of ros, as lc_gen and lc_i are those from ro (cf. Listings 11.1 and 11.2).

Thus, to place for example all LCELLS of RO 9 into the LAB with the floorplan coordinates (26, 5), the following lines are added to the qsf file. The expressions N0 to N3 0 designate, which LE of that LAB should be used; N0 is the topmost LE, N3 0 the bottommost.

Method 2: Using Design Partitions and LogicLock Regions

Another way to enforce the placement of LCELLs into specific LEs makes use of the LogicLock feature of the licensed Quartus II Subscription Edition. The advantage of this method is that the LCELLs can be easily relocated on the FPGA’s floorplan via “drag-and-drop” in the Quartus Chip Planner. This manual procedure, is thus only advisable for moderate amounts of LCELLs.

First, a Design Partition for each entity of the delay-based PUF (here for each RO) has to be created. This can be done in the Chip Planner’s “Design Partitions Window”. Afterwards, a LogicLock Region (LLR) for each Design Partition must be created by right-clicking on the newly created partition entries and selecting “LogicLock Region” ^ “Create New LogicLock Region”. The newly created LLRs are then shown in the Chip Planner’s “LogicLock Region Window”. For the LLR of each RO, set “Size: fixed” and “State: Locked”, allowing to specify their width, height and position. Setting “Reserved: On” determines that no other logic than the corresponding Design Partition is placed in the respective LLR. Then go back to the

Quartos main window and compile the whole project once more. Afterwards, the Chip Planner shows the ROs placed in the defined LLR locations.

However, the placement of the LCELLs within the LEs of an LLR is still determined automatically by the compiler. We may now use the mouse cursor to drag- and-drop the LCELLs from one LE to another, until we have the desired configuration. For each drag-and-drop operation, a “change” is added to the Chip Planner’s “Change Manager” window. This window is also where the button “Check and Save All Netlist Changes” is found. When all drag-and-drop changes have been made, click this button to start another partial compilation that relocates the LCELLs.

A new complete compiler run, however, would always undo these manual changes and one has to go back to the “Change Manager” to reapply them each time. Furthermore, it is not possible to relocate the LLRs keeping the custom LE placement within them. To keep it, one has to go through the following process. First, in the Quartus main window select “Assignments” ^ “Back-Annotate Assignments” ^ “Pin, cell & device assignments”. This saves the current placement of the LCELLs such that they are not undone when the project is compiled again. Then perform another full compiler run and go back to the Chip Planner’s “Design Partitions Window” and for the Design Partition of each RO, set “Netlist Type: Post-Fit” and “Fitter Preservation Level = Placement”. This forces future compiler runs to use the last placement within these Design Partitions. Thus, it is now possible to relocate the LLRs keeping their internal LCELL placement.

When the LLRs are moved to new locations, the previously back-annotated assignments are no longer valid and should be removed. This is done in the Quartus main window by selecting “Assignments” ^ “Remove Assignments” ^ “Pin, Location & Routing Assignments”. Notice though, that this also removes all previous pin assignments; like, e.g. which pins of the FPGA are connected to an external clock, LEDs or push buttons. These have to be redefined in the Quartus Pin Planner. Ideally, all necessary assignments have been exported to a file from which they can easily be imported again.

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