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Power Microelectronics. Device and Process Technologies

Carrier Physics and Junction ElectrostaticsIntroductionCrystal Structure and Energy BandsCarrier Concentration and Fermi LevelIntrinsic SemiconductorExtrinsic SemiconductorCarrier TransportCarrier DriftCarrier DiffusionResistivityBandgap ReductionCarrier RecombinationCarrier LifetimeCarrier Lifetime ControlAuger RecombinationBasic Equations in Semiconductorp-n Junction ElectrostaticsJunction Breakdown PhenomenaAbrupt p+-n JunctionLinearly Graded JunctionPunchthrough PhenomenonJunction TerminationCylindrical JunctionSpherical JunctionFloating Field RingEtched Contour TerminationBevelled Edge TerminationField PlateJunction Termination ExtensionSIPOS (Semi-insulating Polycrystalline Silicon) TerminationSummaryReferencesBipolar Junction DiodeIntroductionBasic Junction Diode TheoryForward ConductionShort-Base DiodeJunction CapacitanceHigh-Voltage p+-n--n+ DiodeForward ConductionReverse BlockingTemperature EffectSchottky Barrier DiodeForward ConductionReverse BlockingOhmic ContactGaAs and SiC Power DiodesSwitching CharacteristicsTurn-on TransientTurn-off TransientMPS (Merged p-i-n/Schottky) DiodeSmart-Power Integrated Synchronous RectifierSummaryReferencesPower Metal-Oxide-Semiconductor Field-Effect TransistorIntroductionBasic MOS PhysicsFlat-Band StateAccumulation StateDepletion StateInversion StateMOS CapacitanceThreshold VoltageStatic CharacteristicsLinear Region OperationSaturation Region OperationMobility DegradationForward BlockingSwitching CharacteristicsTurn-on TransientTurn-off TransientGate ChargeHigh-Frequency OperationParasitic Body Diodedvldt LimitDummy-Gated StructureFolded Gate StructureLateral Radio Frequency (RF) Power MOSFETGraded GateStepped Lateral Double DiffusionPartial Silicon-on-Insulator PlatformPartial SOI Platform FormationParallel and Series OperationsGate Drive CircuitsReferencesInsulated-Gate Bipolar TransistorIntroductionDevice Structure and Current-Voltage CharacteristicsForward Conduction Characteristicsp-i-nIMOSFET ModelBJTIMOSFET ModelOutput ResistanceSwitching CharacteristicsLatch-upTemperature EffectsSeries and Parallel OperationsDevice Operations under Soft SwitchingDual-Gate IGBT for ZV Soft SwitchingLateral IGBT StructureIntegrated Current SensorFabrication AspectsPerformancesDC Measurement in the Linear Operating Region (Switch Operation)DC Measurement in the Saturation Operating RegionTransient ResponseSafe Operating AreaOvercurrent ProtectionVertical IGBT Fabrication ProcessRelated MOS-Bipolar StructuresEmitter Switched Thyristor (EST)Base-Resistance-Controlled Thyristor (BRT)Injection-Enhanced Insulated-Gate BipolarTransistor (IEGT)MOS-Controlled Thyristor (MCT)ReferencesSuperjunction StructuresIntroductionThe Unipolar Ideal Silicon LimitThe Superjunction StructureSJ Electric Field ProfilesCharge ImbalanceFabrication TechnologiesPractical SJ PerformanceThe Practical Concentration EquationPractical SJ Performance EquationPolysilicon Flanked VDMOS (PF VDMOS)Oxide Bypassed (OB) SJ MOSFETGraded Doping in Drift RegionTunable Oxide Bypassed MOSFETsGradient Oxide Bypassed (GOB) StructureLateral Superjunction Power MOSFETDevice Process TechnologyReferencesSilicon Carbide Power DevicesIntroductionSiC Material Properties and Processing TechnologiesMaterial PropertiesProcessing TechnologiesHigh Voltage Designs for SiC DevicesDrift Region and Ideal Breakdown VoltageEdge Termination for SiC Power DevicesSiC RectifiersSiC Schottky Barrier DiodesSiC PIN DiodesSiC Unipolar SwitchesSiC MOSFETsSiC JFETsSiC Bipolar SwitchesSiC BJTs and ThyristorsSiC IGBTsSiC Lateral DevicesReferencesGallium Nitride Power DevicesIntroductionAlGaN/GaN and InGaN/GaN Heterojunction ConfigurationsTheoretical Calculations of Polarization EffectsFor Spontaneous PolarizationFor Piezoelectric PolarizationЗ. Polarization-Induced 2DEG ChargeCalculation of 2DEG Sheet Carrier DensityCalculation of Critical Thickness of Strained LayerSimulation of GaN HEMTsFabrication Induced Trap ChargesNormally-off HEMT Device with Field PlatesCurrent Collapse in GaN HEMTReduction of Current Collapse with Gate Field PlateTemperature EffectsNormally-off Operations in AlGaN/GaN HEMTsHigh Threshold Voltage Normally-off MIS-HEMTsArgon Pre-processed Fluorination Plasma TreatmentHigh Temperature Threshold Voltage StabilityGaN-Based Inverter ConfigurationSummaryReferencesFabrication and Modeling of Power DevicesUnit Process StepsLithographyEtchingDepositionOxidationNonplanarityBird’s Beak FormationImpurity SegregationIon ImplantationChannelingDamageEpitaxyDiffusionBasic Models for the Simulation of Unit Process StepsThermal Oxidation ModelsD ModelD ModelsDiffusion ModelsIon Implantation ModelsAnalytic ModelsMonte Carlo Ion Implant ModelOptical LithographyOptical ComputationsExposureDevelopmentEtchingDepositionAdvances in the Processes for Power DevicesModifications to Improve Gate Oxide Reliability and Breakdown PerformanceUse of Selective Epitaxial Growth for Performance EnhancementReferencesPractical Case Studies in Silicon Power DevicesCase Study I: Process Integration and Design of PFVDMOSProcess Integration to Implement PFVDMOS DeviceSimulation and Process Parameter Determination of PFVDMOS DeviceProcess Parameters and Doping ProfilesSimulation of Off-State PerformanceOn-State Simulation ResultsProcess Sensitivity and Edge TerminationExperimental ResultsProcess Flow and Run SheetsOn- and Off-State Measurement on First Run of PFVDMOSInvestigation of Causes Behind Degraded PerformanceMeasurement on Modified PFVDMOS DevicesAlternatives to PFVDMOSCase Study II:Tunable Oxide Bypass MOSFETSV TOBUMOS FabricationSimulation on 100VTOBUMOSProcess Flow and Cross-SectionsKey Precautions inTOBUMOS FabricationOxide Profile in OB RegionOptimum Doping Profile in Drift RegionOxide Over Etch at TerminationResist-Assisted Etchback Applied on PolySi RemovalAdditional PrecautionsDevice Structure and Mask Layout DesignMask Floorplan and Splits for 100 VTOBUMOS FabricationVTOBUMOS Measurement Results and DiscussionsPhysical Parameter Measurements on Fabricated TOBUMOSTunable Effects on Breakdown Voltage ofTOB-DiodeExperimental Measurement Results on TOBUMOS First RunTuning Effects on TOBUMOSInvestigations for Off-State FailureHot Spot Analysis on TOBUMOSTermination Checks and ModificationsMeasurement Results on New Modified TOBUMOS FabricationReferencesPractical Case Studies in Wide Bandgap Power DevicesCase Study I: Process Integration and Design of SiC DIMOSFETProcess Integration to Self-Aligned SiC DIMOSFETSimulation of a Cell Structure for a Self-Aligned SiC DIMOSFETProcess Parameters and Cell StructureSimulation of the Off-state CharacteristicsSimulation of the On-state CharacteristicsDesign Trade-offsExperimental ResultsProcess Flow, Layout, and Run SheetsOn- and Off-state Measurement on Fabricated 4H-SiC DIMOSFETsCase Study II: Design of Normally-off GaN HEMT for Power Electronics ApplicationsFabrication of Partial AlGaN recess. Metal-Insulator-Semiconductor (MIS) HEMTInnovative Normally-off (MIS) HEMT Structure Using Multi-fluorinated Gate StackObtaining Normally-off (MIS) HEMT Structure Capable of Operating at High Temperature Using Ar and Single F-TreatmentCharacterization of Trap Distribution in the Bandgap Relative to Conduction Band Edge of the Gate Insulator Al2O3Investigation on Methods to Create Deeper Traps to Maintain Reasonable Positive VTH at High Temperature in GaN HEMTsDevice with Process Simplification and Ar Pretreatment of Al2O3 Before F-Plasma Treatment to Create Deeper Electron Traps for High Temperature OperationDetermination of Possible Mechanism That Improves Thermal Stability ofVjH in APT-FPT Devices to Guide Device DesignersConcluding RemarksReferences
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