Device with Process Simplification and Ar Pretreatment of Al2O3 Before F-Plasma Treatment to Create Deeper Electron Traps for High Temperature Operation

The fabrication process flow and the cross-sectional schematic of the device using a single ICP-RIE step to carry out FPTs on Al2O3 dielectric stack are shown in Figs. 11.32 and 11.33, respectively. The device uses the same wafer and structure as in the earlier sections. Only the gate stack is simplified as there is now only one FPT. The Lg, Lgs, Lfp, and Lgd are 3 дш, 5 дш,

  • 1.5 дш, and 5 дш, respectively. The wafer has a standard AlGaN/GaN-on-Si layer structure. The 2DEG carrier density and mobility are 8.5 x 1012cm-2 and 1450cm2/Vs respectively. The first fabrication step of the device is mesa isolation by BCl3-based ICP-RIE. It is followed by SiO2 passivation dielectric deposition by PECVD. Ohmic contacts for source/drain were formed after etching the oxide in the contact regions using multi-metal stack of Ti/Al/Ni/Au with respective thicknesses of 25/125/45/55 nm. Annealing was done by RTA at 850°C for 30 s. After gate patterning, 10 nm (50%) of AlGaN was etched by low power BCl3-based ICP-RIE. This step reduces the 2DEG density to
  • 4.5 x 1012 cm-2 without damaging the AlGaN/GaN interface. This helps preserve carrier mobility in the 2DEG channel (Wang et al., 2015a). 6.5nm of
The fabrication process flow of the normally-off Al2O3/AlGaN/GaN MIS- HEMT with APT-then-FPT gate process

Fig. 11.32. The fabrication process flow of the normally-off Al2O3/AlGaN/GaN MIS- HEMT with APT-then-FPT gate process.

ALD-Al2O3 gate dielectric layer deposition at 250°C was then performed. As dielectric treatments were different for each die, they are separately described. Finally, Ni/Au (15/150 nm) gate-metal deposition followed by annealing at 400° C for 5 min are applied.

Table 11.4 gives summary of how each of the Dies A-E differs. Die A is recess only control device. Die B is only ICP-FPT control device. The ICP-FPT is achieved through ICP-CHF3 plasma treatment with fixed cathode/coil power

The device cross-sectional schematics of the normally-off AlGaN/GaN MIS-HEMT with ICP-fluorinated Al2O3

Fig. 11.33. The device cross-sectional schematics of the normally-off AlGaN/GaN MIS-HEMT with ICP-fluorinated Al2O3. The inset magnifies the gate region, where the fluorine-induced negatively charged ions (F-) and the thickness of Al2O3 gate dielectric stack (q and t2) are shown.

Table 11.4. Processing parameters for the gate dielectric of Dies A-E.

Steps

Die A

Die B

Die C

Die D

Die E

ALD-AI2O3 (thickness t1)

6.5 nm

6.5 nm

6.5 nm

6.5 nm

6.5 nm

Cathode Power (CEP) for APT. Coil Power 100W.

N/A

N/A

50 W

75 W

100W

ICP FPT

N/A

Coil Power 200 W. Low Cathode Power 10 W.

ALD-Al2O3 (thickness t2)

15 nm

15 nm

15 nm

15 nm

15 nm

AFM surface RMS Roughness

0.38 nm

0.53 nm

0.61 nm

0.78 nm

2.29 nm

of 10/200 W for 4 min. Dies C-E have APT before ICP-FPT identical to that of Die B. APT in Dies C, D, and E was done with 20 s ICP-Ar plasma treatment with a fixed coil power of 100 W. This novel step is argon plasma treatment (APT) before FPT.

The APT recipe implemented is based on the existing Al2O3 etching recipe using BCl3/Cl2/Ar ICP-RIE. It uses the same coil power and Ar gas flow as the Al2O3 etching recipe to ensure the amount of dissociated Ar+ is sufficient. The FPT recipe was obtained from various process short-loops. The resulting surface roughness RMS was measured by the AFM to obtain a qualitative signature of trap creation. It is found that by controlling the cathode power of the Argon treatment below 75 W (Die D) is able to preserve the surface roughness RMS within 1 nm. However, if the cathode power of the Ar treatment is increased to 100 W (Die E), the surface roughness RMS will significantly increase from 0.53 nm to 2.29 nm, indicating damage to the AI2O3 surface which will degrade device performance. Due to very large RMS roughness, Die E had much reduced drain current and hence was not analyzed further although it had the highest Vth. Die C had lower Vth than Die D but both had otherwise similar good performance. Hence, detailed studies only focused on Dies A, B, and D.

The process parameters for the gate formation and other process recipes are all included in Table 11.5 in detail. In this table, major process steps are listed first in four columns followed by sub-steps in a run sheet form in three columns to achieve the major steps. Major process steps are numbered as 1, 2(a), 2(b), etc. The sub-steps associated each major process steps are labeled with a dot as 2(b).1, 2(b).2, and so on till all sub-steps are finished. In case these sub-steps are shared between different major process steps, they are included below the very first major process step and reference is made to this in the subsequent major process steps. The structure achieved after some of the major steps is linked to the cross-sections depicted in Fig. 11.32.

As mentioned earlier, detailed studies only focused on Die A, B, and D. The main purpose for comparing three devices is to ensure that plasma treatments for Dies B and D did not degrade the two main performance parameters of on-current and breakdown voltage. The measurements showed that on-current degradation was less than 30% for devices on Die B and D compared to Die A for the same gate overdrive ( Vg - Vth). The breakdown voltages for devices on Dies A, B, and D were measured to be 1110 V, 670 V, and 940 V Clearly, FPT only device has much worse breakdown voltage. APT-FPT device breakdown is less affected compared to Die B. However, as devices on Die A have negative Vth, they are not of much interest in this work. Hence, devices B and D are now compared as regards to ability to create deeper traps and maintain Vth at high temperature of 200° C.

Id-Vg and Vth measurements up to 200°C were performed and Id-Vg characteristics are shown in Fig. 11.34. The reduction in Id is fairly consistent with mobility degradation at high temperature. Vth measurements show that APT-FPT device is able to maintain it at 2.5 V at 200°C. This is the highest reported value using FPT. Moreover, the reduction in Vth of 1.9 V compared to that at room temperature is very low. This shows a good potential for further optimization to raise Vth at higher temperature by increasing its value at room temperature assuming the same 1.9 V reduction can be maintained. The guide to room temperature Vth is provided by the dependence of it on trapped equivalent negative charge in Fig. 11.35.

The low reduction in Vth at high temperature gives a clear evidence that electrons are trapped at much deeper level when APT before FPT is used.

Table 11.5. Major process flow for fluorine-treated normally-off Al2O3/AlGaN/GaN MIS-HEMT fabrication.

Steps

Process

Equipment Used

Process Outcome

1

Wafer Cleaning

Fume Cupboard

Cleaned wafer with particles removed

Sub-steps

Process

Parameters

1.1

Organic

Contamination

Removal

Dip in H2SO4+H2O2 mix (ratio of 3:1) for 2 min; then rinse with DI water

1.2

Native Oxide Removal

Dip in Buffered Oxide Etch (BOE) for 15 s; then rinse with DI water

2(a)

Lithography (Double UV Exposure)

Karl Suss MA6 Mask Aligner

Ti/Al/Ni/Au with thickness of 25/125/45/55 nm

Sub-steps

Process

Parameters

2 (a).1

HMDS spin-coating for adhesion enhancement

3000 rpm for 20 s

2 (a).2

AZ-5214E Photoresist spin-coating

3000 rpm for 20 s

2 (a).3

Photoresist Pre-baking

120°C for 60s

2 (a).4

UV Light Exposure after alignment with the mask pattern

2 s exposure under wavelength = 320 nm

2 (a).5

Photoresist

Post-baking

120° C for 90s

2 (a).6

UV Light Exposure without mask

30 s exposure under wavelength = 320 nm

2 (a).7

Pattern Development

Dip into FHD-5 positive photoresist developer for 50 s

2 (a).8

Lift-off after metal deposition

Dip into acetone and place in ultrasonic cleaner for 20 min

2 (a).9

Acetone Removal

Dip into Iso-Propyl Alcohol (IPA) and placed in ultrasonic cleaner for 10 min

2 (a).10

IPA Removal

Dip into DI water and place in ultrasonic cleaner for 10 min; blow dry with N2 gun

Steps

Process

Equipment Used

Process Outcome

2(b)

Drain/Source

Metal

Deposition

ULVAC EX-400 Electron-beam Film Evaporator

Sub-steps

Process

Comments

2 (b).1

Sample and Crucible Loading

Load the required metal crucibles with sufficient amount of metals within

2 (b).2

Chamber

Vacuuming

Wait until the chamber pressure is under 4 x 10-6 Pa (~2h)

2 (b).3

E-beam location adjustment

Ensure the electron beam is bombarding the surface of the metal crucible

2 (b).4

Metal

Deposition

Carefully control the speed of metal deposition. Ensure the rate is around 0.1 nm/s.

2 (b).5

Crucible Cooling

Allow for about 3 min of cooling time after each deposition before changing the crucible

2 (b).6

Change of Crucible

Change the crucible to the next required metal and repeat from Step 2(b).3.

2 (b).7

Chamber Vent and Sample Unloading

When metal deposition is completed, vent the chamber and unload the sample. Finally, vacuum the chamber after usage to avoid chamber contamination.

  • 2(c)
  • 3

Metal Lift-off Rapid Thermal Annealing

Fume Cupboard BPS Nextral ADAX 60

Formation of ohmic contacts shown in Step 1 of Fig. 11.32

4(a)

Lithography

(Single

Exposure)

Karl Suss MA6 Mask Aligner

~600 nm etched depth in the mesa region

Sub-steps

Process

Parameters

4 (a).1

HMDS spin-coating for adhesion enhancement

3000 rpm for 20 s

Table 11.5. (Continued)

Steps Process

Equipment Used

Process Outcome

4 (a).2 AZ-5214E

Photoresist

spin-coating

3000 rpm for 20 s

4 (a).3 Photoresist Pre-baking

120° C for 90s

4 (a).4 UV Light Exposure after aligned with the mask pattern

30 s exposure under wavelength = 320 nm

4 (a).5 Pattern

Development

Dip into FHD-5 positive photoresist developer for 50 s

4 (a).6 Post-process photoresist removal

Dip into acetone and placed in ultrasonic cleaner for 10 min

4 (a).7 Acetone Removal

Dip into IPA and placed in ultrasonic cleaner for 10 min

4 (a).8 IPA Removal

Dip into DI water and placed in ultrasonic cleaner for 10 min; blow dry with N2 gun

4 (b) Mesa Isolation

STS Multiplex ICP-RIE System

Sub-step 4 (b).1: High Power Etch for fast etching speed

Gas Flow Argon

15 sccm

BCl3

2 sccm

Cl2

8 sccm

Pressure

120 mTorr

Coil Power

100W

Cathode Power

175 W

Etch Time

190s

Sub-step 4 (b).2: Low Power Etch for improved etched surface quality

Gas Flow Argon

15 sccm

BCl3

2 sccm

Cl2

8 sccm

Pressure

120 mTorr

Coil Power

30W

Cathode Power

30W

Etch Time

300s

5 Surface Passivation

Oxford Plasmalab 80 Plus

~200 nm of SiO2

PECVD System

deposited shown in Step 2 of Fig. 11.32

Steps Process

Equipment Used

Process Outcome

Gas Flow N2O

706 sccm

SiH4/N2

158 sccm

Pressure

906 mTorr

RF Power

18 W

Valve Position

26.3 deg

Temperature

300°C

Deposition Time

450 s

6 (a) Lithography (Single UV Exposure)

Karl Suss MA6 Mask Aligner

Follow the same sub-steps 4(a).1 through 4(a).8 of major step 4(a).

200 nm SiO2 etched at the gate

6 (b) Gate Region Opening

STS Multiplex ICP-RIE System

Gas Flow Ar SF6

5 sccm 20 sccm

Pressure

50 mTorr

Coil Power

5W

Cathode Power

100W

Etch Time

330s

7 AlGaN Recess at the Gate Region

STS Multiplex ICP-RIE System

~10 nm of AlGAN etched at the gate shown in

Step 3 of Fig. 11.32

Gas Flow Argon

15 sccm

BCl3

2 sccm

Cl2

8 sccm

Pressure

120 mTorr

Coil Power

30W

Cathode Power

30 W

Etch Time

30s

8 (a) Gate Dielectric Deposition

Savannah 100 ALD system

Plasma-treated Al2O3 gate dielectric shown in Steps 4

and 5 of Fig. 11.32

Gas Flow Trimethylaluminum (TMA) H2O

20 sccm

Temperature

250°C

Thickness per cycle

0.1 nm

Table 11.5. (Continued)

Steps Process

Equipment Used

Process Outcome

8 (b) Plasma Treatments

STS Multiplex ICP-RIE System/Oxford PlasmaPro 80 RIE System

A: RIE Treatment

Gas Flow CHF3

50 sccm

Pressure

37.5 mTorr

RF Power Treatment Time

This is applicable if only RIE treatment is done. Different time variations.

B: ICP-RIE Treatment

Step 1: Argon pre-treatment

Ar

10 sccm

Pressure

15 mTorr

Cathode Power Coil Power

This is applicable only if APT treatment is done by ICP-RIE. Different time variations.

Treatment Time (Variated)

20s

Step 2: Fluorine treatment CHF3

36 sccm

Pressure

37.5 mTorr

Cathode Power

10W

Coil Power

This is applicable

Treatment Time

FPT treatment is done by ICP-RIE. Different time variations.

9 (a) Lithography

Karl Suss MA6 Mask Aligner

(Double UV Exposure)

Ni/Au Contact

Follow the same sub-steps 2(a).1 through 2(a).10 of major step 2(a). (15/150 nm)

Steps

Process

Equipment Used

Process Outcome

9(b)

Gate Metal Deposition

ULVAC EX-400 Electron-beam Film Evaporator

shown in Step 7 of Fig. 11.32

Follow the same sub-steps 2(b).1 through 2(b).10 of major step 2(b).

9(c)

Metal Lift-off

Fume Cupboard

10(a)

Lithography (Single UV Exposure)

STS Multiplex ICP-RIE System

Exposing Pads for device characteriza- . tions shown in Step 8 of Fig. 11.32

Follow the same sub-steps 4(a).1 through 4(a).8 of major step 4(a)

10(b)

Pad Opening

STS Multiplex ICP-RIE System

Sub-step

10 (b).1: Al2O3Etch

Gas Flow

- Ar

10 sccm

BCl3

25 sccm

Pressure

15 mTorr

Coil Power

100W

Cathode Power

175 W

Etch Time

180s

Sub-step 10 (b).12: SiO2Etch

Gas Flow

Ar

5 sccm

SF6

20 sccm

Cl2

8 sccm

Pressure

50 mTorr

Coil Power

5W

Cathode Power

100W

Etch Time

300s

To verify this aspect, the trap characterization was done using the gate stress method described in Sec. 11.2.3.1. Vb in the gate stress measurement ranging from -40 V to 0 V with 5 V increments is applied to obtain the trap density ,Deq mapping for Dies B and D from 0.4 eV to 1.4 eV away from the conduction band energy (Ec) of Al2O3. The extracted trap density is shown in Fig. 11.36. Figure 11.36 also shows the traps that will emit the charge at a given temperature rendering them ineffective in maintaining high Vth. It is clear that the trapped charge density peaks at about 1.02 eV for devices from Die B and a lot of trapped charge is emitted at 200° C. On the other hand, the peak of trapped charge SCD for devices from Die D is located beyond 1.2 eV and these

Id-Vg characteristics of device from Dies B and D (for VD = 1V) at ambienttemperatures of25°C, 100°C, 150°C, and200C

Fig. 11.34. Id-Vg characteristics of device from Dies B and D (for VD = 1V) at ambienttemperatures of25°C, 100°C, 150°C, and200oC.

The relationship between the Qf and the Vh of Dies B-E using the model and comparison with numerical simulations using accurate TCAD tools and measurement

Fig. 11.35. The relationship between the Qf and the Vh of Dies B-E using the model and comparison with numerical simulations using accurate TCAD tools and measurement.

high concentration trapped charges do not de-trap at 200°Cwhich significantly improves high temperature Vth stability.

Although Vth stability at high temperature is credibly established for APT-then-FPT devices, physical mechanism that gives rise to such behavior is not established. A sound scientific reason for such behavior is needed before universality in application of APT prior to FPT can be confirmed. This particular aspect is addressed in Sec. 11.2.3.4.

The fluorine-induced trap state (D-p) distribution along the AI2O3 energy level from the Ec for Dies B and D

Fig. 11.36. The fluorine-induced trap state (D-p) distribution along the AI2O3 energy level from the Ec for Dies B and D.

 
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