Power in Symmetrical Components
The total power in a three-phase network
where Va, Vb, and Vc are phase voltages and Ia, I&, and Ic are line currents. In phase (a),
with similar expressions for phases (b) and (c).
In extending this to cover the total three-phase power it should be noted that
Similarly, I?2, I*1, and I*2 may be replaced.
The total power = 3(Va0I*0 + Va1I*1 + Va2I*2) that is 3 x (the sum of the individual sequence powers in any phase).
Systematic Methods for Fault Analysis in Large Networks
The methods described so far become unwieldy when applied to large networks and a systematic approach utilizing digital computers is used. The generators are represented by their voltages behind the transient reactance, and normally the system is assumed to be on no-load before the occurrence of the three-phase balanced fault. The voltage sources and transient reactances are converted into current sources and the admittance matrix is formed (including the transient reactance admittances). The basic equation [Y][V] = [I] is formed and solved with the constraint that the voltage at the fault node is zero. It is preferable, on grounds of storage and time, not to invert the matrix but to use Gaussian elimination methods. The computation efficiency may also be improved by utilizing the sparsity of the Y matrix. The mesh or loop (impedance matrix) method may be used, although the matrix is not so easily formed.
The following example illustrates a method suitable for determination of balanced three-phase fault currents in a large system by means of a digital computer.
Determine the fault current in the system shown in Figure 7.23(a) for the balanced fault shown.
Figure 7.23 (a) Circuit for Example 7.6 and (b) equivalent circuit. All values are admittances (i.e. -j Y). The generators, that is 1 p.u. voltage behind -j10 p.u. admittance, transform to — j10 p.u. current sources in parallel with — j10 p.u. admittance
The system in Figure 7.23(a) is replaced by the equivalent circuit shown in Figure 7.23(b) by converting a voltage source in series with transient reactance to a current source in parallel with the same reactance. The nodal admittance matrix is then formed. Finally, equation [Y][V] = [I] is formed with VD = 0.0 p.u.
If the bottom row is eliminated and every element is multiplied by 1.5, we get: from which by Gaussian elimination (3 x 1st row + 23 x 2nd row):
Fault MVA = 14.2926 x 100 = 1429.26 MVA
Instead of the nodal admittance method, the bus impedance method may be used for computer fault analysis and has the following advantages:
- 1. Matrix inversion is avoided, resulting in savings in computer storage and time.
- 2. The matrices for the sequences quantities are determined only once and retained for later use; they are readily modified for system changes.
- 3. Mutual impedances between lines are readily handled.
- 4. Subdivisions of the main system may be incorporated.
The system is represented by the usual symmetrical component sequence networks and, frequently, the positive and negative impedances are assumed to be identical. Balanced phase impedances for all items of plant are assumed as are equal voltages for all generators.
In the bus impedance method the network loop matrix, that is [E] = [Z][I], is set up in terms of the various loop currents. First, the buses of interest are short-circuited to the neutral. Consider a fault on one of the buses (k) only, currents in all the other busses short circuited to the neutral will be zero and, from equation [E] = [Z][I], 1.0 = ZkkIk, where Ik = fault current with three-phase symmetrical fault on k. Similarly, the currents with balanced faults on each of the other buses may be easily determined.