Numerical Example

A case of high T_g (above the curing temperature), high-modulus, low-expansion, and 0.05-mm thick underfill

Component 3 Properties	0 (Underfilled Solder)	1 (Chip)	2 (Substrate)
Effective CTE, u, 1/°C	60 x I0“⁶	2.2x10-"	13.2x10-"
Effective Young’s modulus, £, kg/mm²	2000	12300	2000
Poisson's ratio, v	0.40	0.24	0.30
£• Shear modulus G =-.kg/mm² 2(1+ v)	714.3	4959.7	769.2
Thickness./i, mm	0.05	0.5	1.5
Axial compliance X = -—-. min/kg Eh	60.0000 xio-⁴	1.2358 xIO-⁴	2.3333 xlO-⁴
Axial compliance factor (determinant) F — X₀X + + A,2A,o, mm² /kg²		217.0295 xlO-⁸
Thermal forces, kg/mm T„ = 4rl(a₀ - a,)X.₂ + (a₀ - a,)A., ], F T = 4rl(0C\| -a₂)X„ + (ot\| -a„)k₂], F T₂ = =r[(a₂ -a,)X₀ + (a₂ - a₀)X,]. F	150.3194	-620.0493	469.7299
T Normal stresses a = —,kg/mm²h	3006.3880	-1240.0986	313.1533
Interfacial compliance, к, к₀ = —, к, = к, = mm³/kg G₀ 3G, 3G₂	0.7000 x 10^-*	0.3360x10-*	6.5003x10-*

Factor of the relative axial compliance 5 ^F (A,₀ + A'iXA’o + ^2)	0.056858
Chip-to-solder parameter of the interfacial shearing stress / Ao + Xj _i k] = -, mm V ^K0 + ^K1	7.6882
Substrate-to-solder parameter of the interfacial shearing stress IXq + X.₂ _i k₂ =J-, mm Vk„ + k,		2.9423
Parameter of the interfacial shearing stress , kf + kl . 1, J 2кк_г V ^ 2 [kr + klj	8.2057
Shearing stress at chip-solder interface T\| (/) = -ATi. kg/mnr	5087.9305
Shearing stress at solder-PCB interface T:(/) = -ATS.kg/mnr		-3854.4626
Curing temperature 150°C; low temperature -20°C; Change in temperature 170°C;

A case of Low T_g (below the lowest temperature possible), low-modulus, high- expansion, and 0.05-mm thick underfill

Component tt Properties	0 (Underfilled Solder)	1 (Chip)	2 (Substrate)
Effective CTE. u, 1/°C	120 x 10^-6	2.2x10-"	13.2x10-"
Effective Young’s modulus, ft’, kg/mnr	400	12300	2000
Effective Poisson's ratio, v	0.45	0.24	0.30
£ Shear modulus G =-, kg/mnr 2(1+ v) ^c	137.9310	4959.7	769.3
Thickness, ft, mm	0.05	0.5	1.5
Axial compliance X = -——,mm/kg Eh	275x10"⁴	1.2358 xlO^-4	2.3334 x 10^-1
Axial compliance factor F = X()7.i + A,i7.2 + А.2Л.0, mm‘/kg“		984.4136x10-"
Thermal forces, kg/mm To = — [(cto — a,)X₂ + (a₀ — a₂ ], F T — — [(cxi — a₂)Xo + (a, — cto)A,₂], F Ti — — [(Ct₂ — CXi)Xo +(ct₂ — (Xo)Xi]. r	70.2611	-569.8619	499.6008
Normal stress T a = — .kg/mnr h	1405.2220	-1139.7238	333.0672

Interfacial compliance of the components, к, k> h, h₂ 3 „ Ко = —.к, =—,K₂ =-—. mm/kg O₀ jO] jC/₂q	3.6250x10-	0.3360x10-	6.4994x10-
Factor of the axial compliance 6= ^f (Xo + Xi)(A.o +		0.012850
Partial (chip-to-solder) parameter of the interfacial shearing stress IXq + X.j _i fCi=l-. mm K„ + K,		5.5931
Partial (substrate-to-solder) parameter of the interfacial shearing stress /A₀ + A 2 _i k-> = -. mm ]/ K₀ + K₂			3.2995
Parameter of the interfacial shearing stress . k{ + ki , 1. J 2k,k₂ V ^ 2 [kf+kij		9.8427
Shearing stress at chip-solder interface T\|(/) = -kT,, kg/mm²		4061.7032
Shearing stress at solder-PCB interface z₂ (1) = ~kT₂, kg/mm²			-3035.8392
Curing temperature is 150°C; low temperature is -20°C; Change in temperature from the curing temperature to the low temperature is therefore 170'^JC;

A case of high T_? (above the curing temperature), high-modulus, low-expansion, and 0.1-mm thick underfill

Component 9 Properties	0 (Underfilled Solder)	1 (Chip)	2 (Substrate)
Effective CTE, u. 1/°C	60 x 10""	2.2x10-"	13.2x10-"
Effective Young’s modulus, £, kg/mm²	2000	12300	2000
Poisson’s ratio, v	0.40	0.24	0.30
£ Shear modulus G =-.kg/mnr 2(1+ v) ^c	714.3	4959.7	769.2
Thickness, A, mm	0.1	0.5	1.5
Axial compliance A. = * ^ , mm/kg	30.0000x1 O'⁴	1.2358x10-	2.3333x10-
Axial compliance factor F = £₀A.\| + 3.,£₂ + 3.₂3.₀,mm²/kg²		109.9595 x 10"*
Thermal forces, kg/mm T₀ = 4rl(a₀ — a, )X₂ + «x„ -a₂)X,], F T, = ^-[(a, - a₂ )X₀ + (a, - a„ )X₂ ], F 7; = 4й(a, - a, )X„ + (a, - a„ )X, ], F	297.9190	-718.6920	420.7730

Normal stress T 0 = — ,kg/mm²	2979.1900	-1437.3840	280.5153
Interfacial compliance, /in ftl ft, 3 Ko = 7^,K, =— ,K₂=—. mm/kg Oj) JvJ\| JO2	1.4000x1 O'⁴	0.3360 xIO"¹	6.5003 xIO-⁴
Factor of the relative axial compliance 6= ^F (A^ + A,i )(X₀ + A.2)		0.108875
Chip-to-solder parameter of the interfacial shearing stress , /А.О + A.i _i Ко + К,		4.2418
Substrate-to-solder parameter of the interfacial shearing stress , IXo +Л>2 _i k-> = -, mm K₀ + K₂			2.0230
Parameter of the interfacial shearing stress , ? + ! , I, J 2k,k₂ V -1 k = 1 + JI-S ,, ,, , mm . 2 ]l {kr + kij		4.6601
Shearing stress at chip-solder interface x, (/) = -kT_t. kg/mm²		3349.1683
Shearing stress at solder-PCB interface T:(/) = -ATS.kg/mnr			-1960.8443
Curing temperature 150°C; low temperature -20°C; Change in temperature 170°C;

A case of low T_g (below the lowest temperature possible), low-modulus, high-expansion, and 0.1-mm thick underfill

Component 9 Properties	0 (Underfilled Solder)	1 (Chip)	2 (Substrate)
Effective CTE. u, 1/°C	120 xW*	2.2x10-”	13.2х1Г“
Effective Young’s modulus, /:. kg/mnr	400	12300	2000
Effective Poisson’s ratio, v	0.45	0.24	0.30
£ Shear modulus G = , кг/mm²2(1+ v) ^&	137.9310	4959.7	769.3
Thickness, ft, mm	0.1	0.5	1.5
Axial compliance X = * ~ ^v , mm/кг Eh	137.5x lO^-*	1.2358 xIO-⁴	2.3334 xIO-⁴
Axial compliance factor F = A,qA.i + XiT.2 + X2X0, mm‘/kg“	493.6486x IQ-⁸

Thermal forces, kg/mm To — — [((Xo - a, )X-2 + ((Xo — СХ2 )^i ], F T — — [((X\| — a₂)X₀ + (a, — (Xo )^-2 ]■. F Ti — — [(ex2 - (Xi )Xo + (0С2 ^— cto)Xi ]. F	140.1369	-615.6379	475.5010
T Normal stress c= — .kg/mm²h "	1401,3690	-1231.2758	317.0007
Interfacial compliance of the components, к, ho h h₂ 1 „ k₀ = —, к. =-. к, = ——. mm /kg Go 3G\| ' 3G;u	7.2500x10-*	0.3360x10-*	6.4994x10-*
Factor of the axial compliance 6= ^f (Xo + X,)(A.₀ + ^>2)	0.025446
Partial (chip-to-solder) parameter of the interfacial shearing stress , IX 0 + A.1 _I Ko + K\|		4.2765
Partial (substrate-to-solder) parameter of the interfacial shearing stress X₀ + X₂ _i ki =1-. mm K₀ + K₂			3.1891
Parameter of the interfacial shearing stress . kf + k; , 1, J 2k,k₂ V ^ 2 {kf + ki)	5.3190
Shearing stress at chip-solder interface T\|(/> = -A7j, kg/mm²		3274.5560
Shearing stress at solder-PCB interface T₂(/) = -AT,, kg/mm^:			-2529.1898
Curing temperature is 150°C; low temperature is -20°C; Change in temperature from the curing temperature to the low temperature is therefore I70'^JC;

A case of high T_g (above the curing temperature), high-modulus, low-expansion, and 0.75-mm thick underfill

Component $ Properties	0 (Underfilled Solder)	1 (Chip)	2 (Substrate)
Effective CTE, tx, 1/°C	60x10-*	2.2x10"*	13.2x10-*
Effective Young’s modulus, E, kg/mm²	2000	12300	2000
Poisson's ratio, v	0.40	0.24	0.30
£ Shear modulus G =-.kg/mm² 2(1+ v)	714.3	4959.7	769.2
Thickness, A,_mm	0.75	0.5	1.5

1 — v Axial compliance X = ——— ,mm/kg Eh	4.0000x1 O'⁴	1.2358 x 10^-4	2.3333 x 10^-1
Axial compliance factor (determinant) F — A,qA.i + Х1Л.2 + Л.2А.0, mnr /kg"		17.1604 x I0"⁸
Thermal forces, kg/mm T₀ = 4r[(«o - a,»., + (a₀ - a₂)A.,], F T, = ^-[(a, -a₂)X(, +(a, -a₀)X₂], F T₂ = 4rt(«2 -a,)A.₀ + (a, -a₀)X\|], Г	1909.0414	-1771.9806	-137.0608
T Normal stress 0 = —, kg/mm²	2545.3885	-3543.9612	-91.3739
Interfacial compliance, is, ho h hi 1 K₀ = —,K, = —,K₂=—, mm /kg (_/() j(j\| j>J2	10.4998x1 O'⁴	0.3360 xlO"⁴	6.5003 x 10^-1
Factor of the relative axial compliance s ^F (A,₀ + A'lXA’o + ^2)		0.517496
Chip-to-solder parameter of the interfacial shearing . IXo + A.) _1 stress K\| = 1-. mm VKo + K,		0.6951
Substrate-to-solder parameter of the interfacial shearing stress /, - Д0 + Л.2 _mm-i Ko + K₂ ’			0.6104
Parameter of the interfacial shearing stress , .² + f , I, J 2k,k₂ V k= 1 + Jl-S ,, ,, , mm¹. ^ 2 ]l {kr + kij		0.8531
Shearing stress at chip-solder interface X\| (/) = -kTi, kg/mm‘		1511.6946
Shearing stress at solder-PCB interface т ?(/) = -Wi.kg/mm"			-116.9266
Curing temperature 150°C; low temperature -20°C; Change in temperature 170°C;

A case of low T_s (below the lowest temperature possible), low-modulus, high- expansion, and 0.75-mm thick underfill

Component tt Properties	0 (Underfilled Solder)	1 (Chip)	2 (Substrate)
Effective CTE. u, 1/°C	120 x 10"*	2.2 xlO-*	13.2x10-*
Effective Young’s modulus, E, kg/mm²	400	12300	2000
Effective Poisson’s ratio, v	0.45	0.24	0.30
17 Shear modulus G = k<*/mm²2(1 + v) ^&	137.9310	4959.7	769.3
Thickness, ft, mm	0.75	0.5	1.5
1 — V Axial compliance X = ——— ,mm/kg Eli	18.3333 x 10"¹	1.2358 xlO"*	2.3334x10"*

Axial compliance factor F = 2.₀Я.\| + Т.,Я.₂ + 7.₂2.₀,mm²/kg²	68.3188x10-*
Thermal forces, kg/mm T₀ = 4Й(а₀ - a, )X₂ + (ot„ - a₂ )X, ], F T — —[(ocj — a₂)X₀ + (a, — (Xo ]» F T₂ — — [((X2 — 0C1 )A.o + (Ob ^— cco)Xi ]. F	1012.3846	-1185.7792	173.3947
Normal stress а = kg/mm²h	1349.8461	-2371.5584	115.5965
Interfacial compliance of the components, к, ho k /ь , „ k₀ = —. к. =-. к, =——. mm /kg Go 3G\| ' 3G₂₀	54.3750x10-*	0.3360x10-*	6.4994x10-*
Factor of the axial compliance 5 ^F (A,₀ + A.i)(X₀ + X₂)	0.168927
Partial (chip-to-solder) parameter of the interfacial shearine stress ⁺ _mmV Ко + K, '		0.5981
Partial (substrate-to-solder) parameter of the interfacial shearing stress \|Ao + A»2 -1 ki = -. mm V Ко + k₂			0.5827
Parameter of the interfacial shearing stress , f + ki* , 1, J 2k,k, V ^ 2 {kf + kij	0.8163
Shearing stress at chip-solder interface T,(/) = -kT,, kg/mm²		967.9516
Shearing stress at solder-PCB interface T₂(J) = -kT₂, kg/mm²			-141.5421
Curing temperature is 150°C; low temperature is -20°C; Change in temperature from the curing temperature to the low temperature is therefore 170°C;

Calculated stresses (summary)

Stress, kg/mm²		0.05-mm Thick Underfill		0.10-mm Thick Underfill		0.75-mm Thick Underfill
Stress, kg/mm²		HighT,	LowT_e	HighT,	LowT_s	HighT_E	Low T,
Normal stress	in the underfill Co	3006	1405	2979	1401	2545	1350
	in the chip ctj	-1240	-1140	-1437	-1231	-3544	-2372
	in the substrate a₂	313	333	280	317	-91	116
Shearing stress	at the underfill-chip interface Ti	5088	4062	3349	3275	1512	968
Shearing stress	at the underfill- substrate interface T₂	-3854	-3036	-1961	-2529	-117	-141

In the carried out numerical example, the highest shearing stress occurs at the chip-“bond” interface and is by the factor of about 2.45 higher than the maximum shearing stress at the substrate-“bond” interface, but even the latter stress is about twice as high as the stress predicted using the bimaterial model. As to the normal stresses acting in the cross sections of the assembly components, the trimaterial model predicts that the highest stresses occur in the chip, the lowest in the substrate, and that the stresses in the cross sections of the “bond” are not low at all, only about 59% of the normal stresses in the chip (the bimaterial model simply assumes that the normal stresses in the” bond” are zero). The compressive normal stresses in the chip predicted on the basis of the bimaterial model are only about 78% of the stress obtained using the trimaterial model. The normal stresses in the substrate predicted using the bimaterial model are, however, almost twice as high as the trimaterial model predicts, but these stresses are low anyway.

Calculations indicated that the T., level of the underfill material had a significant effect on the induced stresses: the normal stresses in the USCB with a low-modulus (low T) underfill were about half the stresses of the design with high-modulus (high T ) underfill, and this was true for both thin (0.05-mm thick) and thick (0.1- mm thick) USCB layers. As to the role of the USCB thickness, thicker USCBs exhibit somewhat lower normal stresses, than thin layers, but the effect is insignificant. The maximum predicted shearing stresses occur at the USCB/chip, and not at the USCB/substrate interface. This result is in agreement with the observed, in a number of experiments, delaminations at the USCB/chip interface, and not at the USCB/substrate interface. The obtained data also indicate that (in a way, contrary to the current practice) there is an incentive for using low T_s underfills, provided, of course, that their adhesive strength is proven to be sufficient for the lower stress level. This is an important requirement, of course, and might explain why electronic product manufacturers employ mostly high T_? underfills. As to the incentive for using thicker USCBs, the increase in this thickness from 0.05 mm to

0.1 mm resulted in a minor relief in the normal stress in the USCB for both high and low T„ underfills, but led to an appreciable relief in the interfacial stresses at the USCB/chip interface, especially for high T_? underfills: the predicted stress relief in this case was as significant as 34%. For low Tg underfills, the stress relief was much lower, but still appreciable: about 19%. Thicker USCB layers could be more effective, because, as has been shown in our earlier publications and confirmed experimentally, elevated stand-off heights of solder joint interconnections are able to provide appreciable stress relief in the solder material by making the bonding system more compliant. Indeed, for the thickness of 0.75 mm (impossible for FC designs, but rather typical for FPBGA systems) the decrease in the normal stress acting in the USCB cross sections is appreciable, and the decrease in the shearing stress at the USCB/chip interface is as high as 70% in the case of high T_s underfill and even higher, 76%, in the case of low T underfill. The employed analytical stress model used in this analysis can be used for the selection of the adequate underfill material and establishing the appropriate USCB thickness at the design stage. It is noteworthy that, as long as the linear approach is used and the induced stresses are proportional to the change in temperature, the developed model can be used also in situations, when the underfill’s T_? is between the temperature extremes that the assembly of interest experiences during its accelerated testing and in actual operation conditions.

The carried out numerical example shows how the model could be used in practical computations. It shows also that copper lid leads to higher thermally induced stresses than an organic lid. This is true for both the normal stresses in the chip and the maximum interfacial shearing stresses. The developed model can be employed in the analysis of a flip-chip package design of the type in question. Future work should include FEA verifications. The suggested analytical stress model can be particularly helpful when developing an FEA preprocessing model.

The developed analytical thermal stress model can be used for the assessment of the effect of the T_s of the underfill encapsulant and the thickness of the USCB on the induced stresses. The calculations were carried out for two T_s levels, above and below the operation and testing temperature range for the FC or FPBGA assembly with a USCB, and for two thicknesses, 0.05 mm and 0.1 mm, of the USCB. The maximum predicted shearing stresses do indeed occur at the USCB/chip, and not at the USCB/substrate interface, and this result is in agreement with the observed delaminations at the USCB/chip interface.

The calculated data indicate that there is an incentive for using low T_? underfills, provided, of course, that their adhesive strength is proven to be sufficient. This might me less of a challenge, even if the cohesive and the adhesive strength of the USCB layer with a low T_? is not very high, but the applied stresses are also relatively low.

As to the incentive for using thicker USCBs, the increase in this thickness from 0.05 mm to 0.1 mm resulted in rather minor relief in the normal stress in the bond for both high and low T underfills, but led to an appreciable relief in the interfacial stresses at the USCB/chip interface, especially for high T underfills. The stress relief for them was as high as 34%. For low T underfills, the relief was much lower, about 19%. However, for the thickness of 0.75 mm (impossible for FC designs, but quite typical for FPBGA systems), the decrease in the normal stress in the bond is appreciable, and the decrease in the shearing stress at the USCB with the chip is as high as 70% in the case of high T_? underfill and 76% in the case of low T_s underfill.

Thicker USCB layers could be more effective, because, as has been shown earlier, elevated stand-off heights of solder joint interconnections are able to provide appreciable stress relief in the solder joints by making the bond more compliant. This should be attributed in part to the use of solder joints with elevated stand-off heights.

Future work should include FEA evaluations and experimental verification of the obtained information; development of a predictive model for the case when the T_?of the underfill is between the curing and the low temperatures, and for the situation when the dependences of the Young’s modulus and CTE of the underfill are characterized by a nonzero width of the transition region; in effect, the developed model can be used for that; development of a methodology for the evaluation of the role of the viscoelastic behavior of the underfill material; and development of a methodology for the evaluation of the effective modulus and CTE of the USCB layer (this could be done particularly using [26]).